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authorRepository mirror & CI <repomirrorci@gentoo.org>2021-02-25 14:07:27 +0000
committerRepository mirror & CI <repomirrorci@gentoo.org>2021-02-25 14:07:27 +0000
commite766c5ba1c9af5579bc805f62579f424150a7996 (patch)
tree669ac1ee31cf7e14e5c23382ad2b9bbd44a4ca55 /metadata/md5-cache/sci-electronics
parentMerge updates from master (diff)
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2021-02-25 14:07:26 UTC
Diffstat (limited to 'metadata/md5-cache/sci-electronics')
-rw-r--r--metadata/md5-cache/sci-electronics/iverilog-11.04
1 files changed, 2 insertions, 2 deletions
diff --git a/metadata/md5-cache/sci-electronics/iverilog-11.0 b/metadata/md5-cache/sci-electronics/iverilog-11.0
index 55c79385c750..98505b60fcf4 100644
--- a/metadata/md5-cache/sci-electronics/iverilog-11.0
+++ b/metadata/md5-cache/sci-electronics/iverilog-11.0
@@ -4,10 +4,10 @@ DEPEND=sys-libs/readline:= sys-libs/zlib
DESCRIPTION=A Verilog simulation and synthesis tool
EAPI=7
HOMEPAGE=http://iverilog.icarus.com https://github.com/steveicarus/iverilog
-KEYWORDS=~alpha ~amd64 ~arm ~arm64 ~hppa ~ia64 ~m68k ~mips ~ppc ~ppc64 ~riscv ~s390 ~sparc ~x86
+KEYWORDS=~alpha ~amd64 ~arm ~arm64 ~hppa ~ia64 ~m68k ~mips ~ppc ~ppc64 ~riscv ~s390 ~sparc x86
LICENSE=LGPL-2.1
RDEPEND=sys-libs/readline:= sys-libs/zlib
SLOT=0
SRC_URI=https://github.com/steveicarus/iverilog/archive/v11_0.tar.gz -> iverilog-11.0.tar.gz
_eclasses_=autotools 9988ecbe04129214297a7bbf3d253710 libtool f143db5a74ccd9ca28c1234deffede96 multilib d410501a125f99ffb560b0c523cd3d1e toolchain-funcs 24921b57d6561d87cbef4916a296ada4
-_md5_=41050673a7687e7dd50d5327faebc4f4
+_md5_=79d31add1eca9c5500a4aba072c9d090