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| author |   Repository mirror & CI <repomirrorci@gentoo.org> | 2020-01-07 07:05:59 +0000 |
|---|---|---|
| committer | Repository mirror & CI <repomirrorci@gentoo.org> | 2020-01-07 07:05:59 +0000 |
| commit | 8790162db527945b22386fe97cc395e42e3c8f0c (patch) | |
| tree | d781e91af6a7c7bac6f7a3664cafb05c3d91a66c /metadata/md5-cache/sci-electronics | |
| parent | Merge updates from master (diff) | |
| download | gentoo-8790162db527945b22386fe97cc395e42e3c8f0c.tar.gz gentoo-8790162db527945b22386fe97cc395e42e3c8f0c.tar.bz2 gentoo-8790162db527945b22386fe97cc395e42e3c8f0c.zip | |
2020-01-07 07:05:59 UTC
Diffstat (limited to 'metadata/md5-cache/sci-electronics')
| -rw-r--r-- | metadata/md5-cache/sci-electronics/iverilog-10.3 | 2 | ||||
| -rw-r--r-- | metadata/md5-cache/sci-electronics/iverilog-9999 | 13 |
2 files changed, 14 insertions, 1 deletions
diff --git a/metadata/md5-cache/sci-electronics/iverilog-10.3 b/metadata/md5-cache/sci-electronics/iverilog-10.3 index ad9ce47c0a27..b25034b91f2b 100644 --- a/metadata/md5-cache/sci-electronics/iverilog-10.3 +++ b/metadata/md5-cache/sci-electronics/iverilog-10.3 @@ -11,4 +11,4 @@ RDEPEND=sys-libs/readline:0 sys-libs/zlib SLOT=0 SRC_URI=https://github.com/steveicarus/iverilog/archive/v10_3.tar.gz -> iverilog-10.3.tar.gz _eclasses_=autotools ea7865c8fba1ea8d3639f355fffe1a3c libtool f143db5a74ccd9ca28c1234deffede96 multilib 1d91b03d42ab6308b5f4f6b598ed110e toolchain-funcs 512eb3367f507ebaa1d1d43ab7d66e6c -_md5_=6f460cfe46c105c517a305b6a07d7d5c +_md5_=4611de40096aeefee1484ed1e55c1b3b diff --git a/metadata/md5-cache/sci-electronics/iverilog-9999 b/metadata/md5-cache/sci-electronics/iverilog-9999 new file mode 100644 index 000000000000..485d4695e5ef --- /dev/null +++ b/metadata/md5-cache/sci-electronics/iverilog-9999 @@ -0,0 +1,13 @@ +BDEPEND=>=app-portage/elt-patches-20170815 || ( >=sys-devel/automake-1.16.1:1.16 >=sys-devel/automake-1.15.1:1.15 ) >=sys-devel/autoconf-2.69 >=sys-devel/libtool-2.4 >=dev-vcs/git-1.8.2.1[curl] +DEFINED_PHASES=install prepare unpack +DEPEND=dev-util/gperf sys-libs/readline:0 sys-libs/zlib +DESCRIPTION=A Verilog simulation and synthesis tool +EAPI=7 +HOMEPAGE=http://iverilog.icarus.com https://github.com/steveicarus/iverilog +IUSE=examples +LICENSE=LGPL-2.1 +PROPERTIES=live +RDEPEND=sys-libs/readline:0 sys-libs/zlib +SLOT=0 +_eclasses_=autotools ea7865c8fba1ea8d3639f355fffe1a3c git-r3 7d6c351ee8b1feb12ed8c8b0adae088b libtool f143db5a74ccd9ca28c1234deffede96 multilib 1d91b03d42ab6308b5f4f6b598ed110e toolchain-funcs 512eb3367f507ebaa1d1d43ab7d66e6c +_md5_=4611de40096aeefee1484ed1e55c1b3b |