sci-electronics/yosys: new package, add 0.32, 0.40

Signed-off-by: Huang Rui <vowstar@gmail.com>

5 files changed, 343 insertions, 0 deletions

diff --git a/sci-electronics/yosys/Manifest b/sci-electronics/yosys/Manifest
new file mode 100644
index 000000000..c8d83d0af
--- /dev/null
+++ b/sci-electronics/yosys/Manifest
@@ -0,0 +1,4 @@
+DIST abc-0cd90d0d2c5338277d832a1d890bed286486bcf5.tar.gz 6154902 BLAKE2B 1767891c9ae76aa0baea85a26a22dace92912affe857f9637abc90827b3193e2cf736e7b81cb2c3e56d80d76a98220863e0669fff5df9fa86ee4c990c594edd2 SHA512 7233edda97b6a2dfbb285b1884befc515b246392050cf01ae623c6bac4b4203cd667022f2fda21c068efc3d72a9fe50c3a66a2f16399fe959bea95f33e305f94
+DIST abc-bb64142b07794ee685494564471e67365a093710.tar.gz 6119314 BLAKE2B 6cba6362e59bb766d784a1c9edeca8906bf2b08df79d44a16ddb69c72c30e57c95a8375e0b0bad489c35a9a3728c1ccdd1b7fe84d5f5f48f113d59f7615aab8d SHA512 74d1c7c4b204fe30e85e31ed837feadbda9759afd9703ad525a1de53cb704d0f59ac25f78b918e3003fbc87b3afd293d138e0cfc1b38df9139a9aea8f5737fe7
+DIST yosys-0.32.tar.gz 2552341 BLAKE2B 491cd92de29097f3f9baca4c0982acc7fa180ae3b4ee5980b5246618520b3b0d53f0489615fba903838daef35b7a676106ef8b56e6f22ccc5e927429174dc4ac SHA512 3704ca8286e93ca53344b2a518ba4f2b9c137cf9688a95863f691cce3cca761d061100d3b93a0ad1dbabda13c0dbb137c5234abb6675ce2e5b5167701ccb0910
+DIST yosys-0.40.tar.gz 2802706 BLAKE2B d44a436b48bb0c65f67ee398a1663f309e169a22d1a55a0ac46ba60c6fbe9d60a31476e577c091c11bfec687491885df94db6ab6e6c135c014f813f9f7fb7811 SHA512 b42afbd9f4d65fe81110c0516e1d5d2cb8accc7fcc8f5bc79887d788547bab74292933b062405cf7c93c74311ad633a12c2ee11be55d7a803445dfac372937cd
diff --git a/sci-electronics/yosys/files/yosys-0.31-abc-c++17-fix.patch b/sci-electronics/yosys/files/yosys-0.31-abc-c++17-fix.patch
new file mode 100644
index 000000000..1dad9e6ee
--- /dev/null
+++ b/sci-electronics/yosys/files/yosys-0.31-abc-c++17-fix.patch
@@ -0,0 +1,226 @@
+--- yosys-yosys-0.31/abc/src/misc/zlib/trees.c	2023-06-28 02:10:24.000000000 -0700
++++ yosys-yosys-0.31/abc/src/misc/zlib/trees.c	2023-07-18 08:56:03.335795722 -0700
+@@ -1144,7 +1144,7 @@
+  */
+ local unsigned bi_reverse(unsigned code, int len)
+ {
+-    register unsigned res = 0;
++    unsigned res = 0;
+     do {
+         res |= code & 1;
+         code >>= 1, res <<= 1;
+--- yosys-yosys-0.31/abc/src/misc/zlib/crc32.c	2023-06-28 02:10:24.000000000 -0700
++++ yosys-yosys-0.31/abc/src/misc/zlib/crc32.c	2023-07-18 08:55:38.138798430 -0700
+@@ -269,8 +269,8 @@
+ /* ========================================================================= */
+ local unsigned long crc32_little(unsigned long crc, const unsigned char FAR *buf, unsigned len)
+ {
+-    register u4 c;
+-    register const u4 FAR *buf4;
++    u4 c;
++    const u4 FAR *buf4;
+ 
+     c = (u4)crc;
+     c = ~c;
+@@ -306,8 +306,8 @@
+ /* ========================================================================= */
+ local unsigned long crc32_big(unsigned long crc, const unsigned char FAR *buf, unsigned len)
+ {
+-    register u4 c;
+-    register const u4 FAR *buf4;
++    u4 c;
++    const u4 FAR *buf4;
+ 
+     c = REV((u4)crc);
+     c = ~c;
+--- yosys-yosys-0.31/abc/src/misc/zlib/deflate.c	2023-06-28 02:10:24.000000000 -0700
++++ yosys-yosys-0.31/abc/src/misc/zlib/deflate.c	2023-07-18 08:55:10.870801362 -0700
+@@ -1027,9 +1027,9 @@
+ local uInt longest_match(deflate_state *s, IPos cur_match)
+ {
+     unsigned chain_length = s->max_chain_length;/* max hash chain length */
+-    register Bytef *scan = s->window + s->strstart; /* current string */
+-    register Bytef *match;                       /* matched string */
+-    register int len;                           /* length of current match */
++    Bytef *scan = s->window + s->strstart; /* current string */
++    Bytef *match;                       /* matched string */
++    int len;                           /* length of current match */
+     int best_len = s->prev_length;              /* best match length so far */
+     int nice_match = s->nice_match;             /* stop if match long enough */
+     IPos limit = s->strstart > (IPos)MAX_DIST(s) ?
+@@ -1044,13 +1044,13 @@
+     /* Compare two bytes at a time. Note: this is not always beneficial.
+      * Try with and without -DUNALIGNED_OK to check.
+      */
+-    register Bytef *strend = s->window + s->strstart + MAX_MATCH - 1;
+-    register ush scan_start = *(ushf*)scan;
+-    register ush scan_end   = *(ushf*)(scan+best_len-1);
++    Bytef *strend = s->window + s->strstart + MAX_MATCH - 1;
++    ush scan_start = *(ushf*)scan;
++    ush scan_end   = *(ushf*)(scan+best_len-1);
+ #else
+-    register Bytef *strend = s->window + s->strstart + MAX_MATCH;
+-    register Byte scan_end1  = scan[best_len-1];
+-    register Byte scan_end   = scan[best_len];
++    Bytef *strend = s->window + s->strstart + MAX_MATCH;
++    Byte scan_end1  = scan[best_len-1];
++    Byte scan_end   = scan[best_len];
+ #endif
+ 
+     /* The code is optimized for HASH_BITS >= 8 and MAX_MATCH-2 multiple of 16.
+@@ -1173,10 +1173,10 @@
+  */
+ local uInt longest_match(deflate_state *s, IPos cur_match)
+ {
+-    register Bytef *scan = s->window + s->strstart; /* current string */
+-    register Bytef *match;                       /* matched string */
+-    register int len;                           /* length of current match */
+-    register Bytef *strend = s->window + s->strstart + MAX_MATCH;
++    Bytef *scan = s->window + s->strstart; /* current string */
++    Bytef *match;                       /* matched string */
++    int len;                           /* length of current match */
++    Bytef *strend = s->window + s->strstart + MAX_MATCH;
+ 
+     /* The code is optimized for HASH_BITS >= 8 and MAX_MATCH-2 multiple of 16.
+      * It is easy to get rid of this optimization if necessary.
+@@ -1261,8 +1261,8 @@
+  */
+ local void fill_window(deflate_state *s)
+ {
+-    register unsigned n, m;
+-    register Posf *p;
++    unsigned n, m;
++    Posf *p;
+     unsigned more;    /* Amount of free space at the end of the window. */
+     uInt wsize = s->w_size;
+ 
+--- yosys-yosys-0.31/abc/src/misc/extra/extraUtilUtil.c	2023-06-28 02:10:24.000000000 -0700
++++ yosys-yosys-0.31/abc/src/misc/extra/extraUtilUtil.c	2023-07-18 08:53:09.857814372 -0700
+@@ -97,8 +97,8 @@
+ ***********************************************************************/
+ int Extra_UtilGetopt( int argc, char *argv[], const char *optstring )
+ {
+-    register int c;
+-    register const char *place;
++    int c;
++    const char *place;
+ 
+     globalUtilOptarg = NULL;
+ 
+--- yosys-yosys-0.31/abc/src/misc/bzlib/compress.c	2023-06-28 02:10:24.000000000 -0700
++++ yosys-yosys-0.31/abc/src/misc/bzlib/compress.c	2023-07-18 08:54:26.994806079 -0700
+@@ -190,15 +190,15 @@
+             zPend = 0;
+          }
+          {
+-            register UChar  rtmp;
+-            register UChar* ryy_j;
+-            register UChar  rll_i;
++            UChar  rtmp;
++            UChar* ryy_j;
++            UChar  rll_i;
+             rtmp  = yy[1];
+             yy[1] = yy[0];
+             ryy_j = &(yy[1]);
+             rll_i = ll_i;
+             while ( rll_i != rtmp ) {
+-               register UChar rtmp2;
++               UChar rtmp2;
+                ryy_j++;
+                rtmp2  = rtmp;
+                rtmp   = *ryy_j;
+@@ -360,8 +360,8 @@
+ 
+          if (nGroups == 6 && 50 == ge-gs+1) {
+             /*--- fast track the common case ---*/
+-            register UInt32 cost01, cost23, cost45;
+-            register UInt16 icv;
++            UInt32 cost01, cost23, cost45;
++            UInt16 icv;
+             cost01 = cost23 = cost45 = 0;
+ 
+ #           define BZ_ITER(nn)                \
+--- yosys-yosys-0.31/abc/src/bdd/cudd/cuddSat.c	2023-06-28 02:10:24.000000000 -0700
++++ yosys-yosys-0.31/abc/src/bdd/cudd/cuddSat.c	2023-07-18 08:59:43.372772066 -0700
+@@ -279,7 +279,7 @@
+   DdNode * f,
+   int * length)
+ {
+-    register    DdNode  *F;
++       DdNode  *F;
+     st__table    *visited;
+     DdNode      *sol;
+     cuddPathPair *rootPair;
+@@ -351,7 +351,7 @@
+   DdNode * f,
+   int * weight)
+ {
+-    register    DdNode  *F;
++       DdNode  *F;
+     st__table    *visited;
+     cuddPathPair *my_pair;
+     int         complement, cost;
+--- yosys-yosys-0.31/abc/src/bdd/cudd/cuddSplit.c	2023-06-28 02:10:24.000000000 -0700
++++ yosys-yosys-0.31/abc/src/bdd/cudd/cuddSplit.c	2023-07-18 08:59:42.987772107 -0700
+@@ -638,8 +638,8 @@
+ {
+ 
+     DdNode *N,*Nv,*Nnv;
+-    register double min_v,min_nv;
+-    register double min_N;
++    double min_v,min_nv;
++    double min_N;
+     double *pmin;
+     double *dummy;
+ 
+--- yosys-yosys-0.31/abc/src/bdd/cudd/cuddCache.c	2023-06-28 02:10:24.000000000 -0700
++++ yosys-yosys-0.31/abc/src/bdd/cudd/cuddCache.c	2023-07-18 08:58:14.403781631 -0700
+@@ -229,7 +229,7 @@
+ {
+     int posn;
+     unsigned hash;
+-    register DdCache *entry;
++    DdCache *entry;
+     ptruint uf, ug, uh;
+     ptruint ufc, ugc, uhc;
+ 
+@@ -283,7 +283,7 @@
+ {
+     int posn;
+     unsigned hash;
+-    register DdCache *entry;
++    DdCache *entry;
+ 
+     hash = ddCHash2_(op,cuddF2L(f),cuddF2L(g));
+ //    posn = ddCHash2(op,cuddF2L(f),cuddF2L(g),table->cacheShift);
+@@ -328,7 +328,7 @@
+ {
+     int posn;
+     unsigned hash;
+-    register DdCache *entry;
++    DdCache *entry;
+ 
+     hash = ddCHash2_(op,cuddF2L(f),cuddF2L(f));
+ //    posn = ddCHash2(op,cuddF2L(f),cuddF2L(f),table->cacheShift);
+--- yosys-yosys-0.31/abc/src/bdd/cudd/cuddBddIte.c	2023-06-28 02:10:24.000000000 -0700
++++ yosys-yosys-0.31/abc/src/bdd/cudd/cuddBddIte.c	2023-07-18 08:58:13.834781692 -0700
+@@ -1203,8 +1203,8 @@
+   unsigned int * topgp,
+   unsigned int * tophp)
+ {
+-    register DdNode             *F, *G, *H, *r, *f, *g, *h;
+-    register unsigned int       topf, topg, toph;
++    DdNode             *F, *G, *H, *r, *f, *g, *h;
++    unsigned int       topf, topg, toph;
+     DdNode                      *one = dd->one;
+     int                         comple, change;
+ 
+@@ -1305,7 +1305,7 @@
+   unsigned int * topgp,
+   unsigned int * tophp)
+ {
+-    register DdNode             *r, *f, *g, *h;
++    DdNode             *r, *f, *g, *h;
+     int                         comple, change;
+ 
+     f = *fp;
diff --git a/sci-electronics/yosys/metadata.xml b/sci-electronics/yosys/metadata.xml
new file mode 100644
index 000000000..a51a517ef
--- /dev/null
+++ b/sci-electronics/yosys/metadata.xml
@@ -0,0 +1,29 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE pkgmetadata SYSTEM "https://www.gentoo.org/dtd/metadata.dtd">
+<pkgmetadata>
+	<maintainer type="person">
+		<email>vowstar@gmail.com</email>
+		<name>Huang Rui</name>
+	</maintainer>
+	<upstream>
+		<remote-id type="github">YosysHQ/yosys</remote-id>
+	</upstream>
+	<longdescription lang="en">
+		This is a framework for RTL synthesis tools. It currently has extensive
+		Verilog-2005 support and provides a basic set of synthesis algorithms
+		for various application domains.
+		Yosys can be adapted to perform any synthesis job by combining the
+		existing passes (algorithms) using synthesis scripts and adding
+		additional passes as needed by extending the yosys C++ code base.
+		Yosys is free software licensed under the ISC license (a GPL compatible
+		license that is similar in terms to the MIT license or the 2-clause BSD
+		license).
+	</longdescription>
+	<longdescription lang="zh">
+		这是一个针对RTL合成工具的框架。它目前广泛支持Verilog-2005，并提供一套
+		基础的合成算法用于多种应用领域。Yosys可以通过组合现有的合成脚本中的算法，
+		并根据需要扩展Yosys的C++代码库来添加额外的算法，从而适应任何合成任务。
+		Yosys是根据ISC许可证发布的免费软件，这是一种与GPL兼容的许可证，其条款与
+		MIT许可证或二条款BSD许可证类似。
+	</longdescription>
+</pkgmetadata>
diff --git a/sci-electronics/yosys/yosys-0.32.ebuild b/sci-electronics/yosys/yosys-0.32.ebuild
new file mode 100644
index 000000000..724268c96
--- /dev/null
+++ b/sci-electronics/yosys/yosys-0.32.ebuild
@@ -0,0 +1,44 @@
+# Copyright 1999-2024 Gentoo Authors
+
+EAPI=8
+
+# get the current value from the yosys makefile...look for ABCREV
+ABC_GIT_COMMIT=bb64142b07794ee685494564471e67365a093710
+
+DESCRIPTION="framework for Verilog RTL synthesis"
+HOMEPAGE="http://www.clifford.at/yosys/"
+SRC_URI="
+	https://github.com/YosysHQ/${PN}/archive/${P}.tar.gz
+	https://github.com/YosysHQ/abc/archive/${ABC_GIT_COMMIT}.tar.gz -> abc-${ABC_GIT_COMMIT}.tar.gz
+"
+S="${WORKDIR}/${PN}-${PN}-${PV}"
+LICENSE="ISC"
+SLOT="0"
+KEYWORDS="~amd64"
+
+RDEPEND="
+	dev-libs/boost
+	media-gfx/xdot
+	sys-devel/clang
+"
+
+DEPEND="${RDEPEND}"
+BDEPEND="dev-vcs/git"
+
+PATCHES=(
+	"${FILESDIR}/${PN}-0.31-abc-c++17-fix.patch"
+)
+
+QA_PRESTRIPPED="
+	/usr/bin/yosys-filterlib
+	/usr/bin/yosys-abc
+"
+
+src_prepare() {
+	mv "${WORKDIR}/abc-${ABC_GIT_COMMIT}" "${S}"/abc || die
+	default
+}
+
+src_install() {
+	emake DESTDIR="${D}" PREFIX='/usr' install
+}
diff --git a/sci-electronics/yosys/yosys-0.40.ebuild b/sci-electronics/yosys/yosys-0.40.ebuild
new file mode 100644
index 000000000..199e87052
--- /dev/null
+++ b/sci-electronics/yosys/yosys-0.40.ebuild
@@ -0,0 +1,40 @@
+# Copyright 1999-2024 Gentoo Authors
+
+EAPI=8
+
+# get the current value from the yosys makefile...look for ABCREV
+ABC_GIT_COMMIT=0cd90d0d2c5338277d832a1d890bed286486bcf5
+
+DESCRIPTION="framework for Verilog RTL synthesis"
+HOMEPAGE="http://www.clifford.at/yosys/"
+SRC_URI="
+	https://github.com/YosysHQ/${PN}/archive/${P}.tar.gz
+	https://github.com/YosysHQ/abc/archive/${ABC_GIT_COMMIT}.tar.gz -> abc-${ABC_GIT_COMMIT}.tar.gz
+"
+S="${WORKDIR}/${PN}-${PN}-${PV}"
+LICENSE="ISC"
+SLOT="0"
+KEYWORDS="~amd64"
+
+RDEPEND="
+	dev-libs/boost
+	media-gfx/xdot
+	sys-devel/clang
+"
+
+DEPEND="${RDEPEND}"
+BDEPEND="dev-vcs/git"
+
+QA_PRESTRIPPED="
+	/usr/bin/yosys-filterlib
+	/usr/bin/yosys-abc
+"
+
+src_prepare() {
+	mv "${WORKDIR}/abc-${ABC_GIT_COMMIT}" "${S}"/abc || die
+	default
+}
+
+src_install() {
+	emake DESTDIR="${D}" PREFIX='/usr' install
+}