Preparations for linux-kernel 3.7

Package-Manager: portage-2.2.0_alpha142/cvs/Linux x86_64
Manifest-Sign-Key: 0x62EEF090

4 files changed, 614 insertions, 32 deletions

diff --git a/sys-power/phc-intel/ChangeLog b/sys-power/phc-intel/ChangeLog
index 513e5f150471..7d84189e49aa 100644
--- a/sys-power/phc-intel/ChangeLog
+++ b/sys-power/phc-intel/ChangeLog
@@ -1,6 +1,12 @@
 # ChangeLog for sys-power/phc-intel
 # Copyright 1999-2012 Gentoo Foundation; Distributed under the GPL v2
-# $Header: /var/cvsroot/gentoo-x86/sys-power/phc-intel/ChangeLog,v 1.9 2012/05/24 05:47:16 vapier Exp $
+# $Header: /var/cvsroot/gentoo-x86/sys-power/phc-intel/ChangeLog,v 1.10 2012/11/15 01:08:43 xmw Exp $
+
+*phc-intel-0.3.2.12.1-r4 (15 Nov 2012)
+
+  15 Nov 2012; Michael Weber <xmw@gentoo.org> +phc-intel-0.3.2.12.1-r4.ebuild,
+  +files/phc-intel-0.3.2.12.1-3.7.patch:
+  Preparations for linux-kernel 3.7
 
   24 May 2012; Mike Frysinger <vapier@gentoo.org>
   phc-intel-0.3.2.12.1-r3.ebuild:
diff --git a/sys-power/phc-intel/Manifest b/sys-power/phc-intel/Manifest
index 517c9ba3eb29..94acbe4a363d 100644
--- a/sys-power/phc-intel/Manifest
+++ b/sys-power/phc-intel/Manifest
@@ -1,31 +1,13 @@
------BEGIN PGP SIGNED MESSAGE-----
-Hash: SHA1
-
-AUX phc-intel-0.3.2.12.1-2.6.35.patch 16066 RMD160 9258ab48af55b30e69ac484331b3e1799a04ec06 SHA1 f768fa0ab033ad715f0a2830e9b0a5eecf6b79fa SHA256 02bfdb717629025e505c4575afe89c465ef47755223a5577842d6db3fef8e427
-AUX phc-intel-0.3.2.12.1-2.6.36.patch 15934 RMD160 4a67d9be09f8471525aa4c619fb4b215337dfdd5 SHA1 85f7230f714e8f21b61a5ca96367fcfe340bf070 SHA256 9310783980d12ababb1a5aaddd7ad2cf0c1f2f5a749a89cc32b33cfef9e49c28
-AUX phc-intel-0.3.2.12.1-2.6.37.patch 15919 RMD160 641e5bb542123c54a08297344f265692e5554eb0 SHA1 72147d7586470b9ad15655b06c5d16f3787fe1fa SHA256 3a58b6e56707a0b136507607818b8b58e106b1e5872c0b5b833fbddcb7c1d873
-DIST phc-intel-0.3.199.3_pre.tar.bz2 15508 RMD160 0348c0776f11beda14befbdfaf2f246516e68558 SHA1 b51c7d6123c1a45dcf7cd54273ce642ef8f7895a SHA256 4441af7a0a1335a920b0d18a46483a64fbae8e57d98a6bdbf31dbacac2bbdf82
-DIST phc-intel-0.3.2.10.tar.bz2 20680 RMD160 c9af322d7234c83aef348eb1b01cccf1f5cb1b18 SHA1 3e8b3e2f5732ace6e76146bd820448fd17369c31 SHA256 8483e071ad2644c339539ac5298c7a31a12212fd9a68baa1f6766dad146510f5
-DIST phc-intel-0.3.2.12.1.tar.bz2 14412 RMD160 d8a8ca003f0af2d1f8e7a59ab8739a51afceafd3 SHA1 d5c991376f7ce7f3b7afa6fc7618b4ba602bf457 SHA256 4f66989d424d328b205873da1b0363e75f27d7912e0e93c1cad3407c17be8264
-EBUILD phc-intel-0.3.199.3_pre.ebuild 1201 RMD160 bcace92a9dac5f7fcb9a18a3d9d2a196cc3c00da SHA1 787d5420553c6c6c979a9e0b8eb39a229679150a SHA256 cf022fadc97cd3b56ed3888b9f645d8943447a741627b2d80e19cb315147a1c0
-EBUILD phc-intel-0.3.2.10.ebuild 1079 RMD160 aff8b2924d4878da10ec374d9c8c179a3c1d6d23 SHA1 5c445495287110484664ce0312d539e8f170ec21 SHA256 19ed93eab1feeb9cd3aa214ba76ff5834cff06cb821676842574e6075f8a92c4
-EBUILD phc-intel-0.3.2.12.1-r3.ebuild 1696 RMD160 c02e0b48defe1a30ed899fe5a09a5f81c8cf8d25 SHA1 9875d674b0a58c88c3010de339a8497bdc287cb9 SHA256 e1b3824ce44d78d60a9a906e10c4a4ddc28c9d0c4e2cdaf8afe536e956944fe0
-MISC ChangeLog 1898 RMD160 60c34470bc53498485e33bdba931f9904ee1dce1 SHA1 610af7d08428c61546dfc546918c2d4ae3a7749c SHA256 87e0ee8ff1971f9933073464a9c867d311bb59522fffe0a502ebf5fe95e6c58b
-MISC metadata.xml 223 RMD160 ece0d9320b4ad1fdb29d1dec4f85e84ffda0d863 SHA1 325a16f4c96d533e8642c26ab395b06ab42f51b5 SHA256 89097f936927d56068988263e382edb683f359b27293955708e9ade4d256220d
------BEGIN PGP SIGNATURE-----
-Version: GnuPG v2.0.19 (GNU/Linux)
-
-iQIcBAEBAgAGBQJPvcu3AAoJELEHsLL7fEFWdJcP/3UnBom3bbdh+26QzW0jZO45
-9rsV513ZI/igTrkcIsMBNJ9DsBRqEDpcs1zrHlB5E+Q+F4wH9Rxze7XkCU2N4jQq
-ZLSxhx4+fNxJ5Yz0TpmVheLRZ6oAvRrGrwDElVN1vpEMNcQfULftuAaksIJzY76Q
-GQkBDkenzeTmrjOAQKajkeCFdh3dUjjePhDFgU/6G1D+MsevCQOZAD4IeCN5hZ3R
-7vyIAbA/+eIgkn4tj+eZw+YCDlISQS47l2ZVLKp2OYNv8lSebLvYQxOhmx4ixEn4
-CxECzUHP2pZZGKbvKaYNS+jEyQ/gmS/AfqFnci8pXRRsxl8ZKHDo5HbbyhVBZB8R
-3dqdEd9tKN/oSLNJV1XWL6OGXieHX6ZDiXbeo3UFURc+rIfUHuF+dbr3VmL5mu5s
-sTLO2AX+9qV0te3BiCf8uGMIOhnE8AiN7XcYd2qirY3YSsIS9dasTublwt5uYbRJ
-slZ9XwDNT3WjKntggLUnvA4ideTrew1cNuDFUj2Kdd1/GFPx4EC7HHiuaKjvAVcz
-mMAcb0sknUVBuYmjHZZ+TsOJXeUpO/TmGO7iSkZgCDBwZ4Rq3jphMZKYDT4vWmrk
-XRuisqNpTvzUf3FFjHFM05vyH4B/yoLjbrrtQeTTJMxh7JrQHbwyROAXAH18KURw
-4UboQ8txKJIgvVxqLsEG
-=Irj1
------END PGP SIGNATURE-----
+AUX phc-intel-0.3.2.12.1-2.6.35.patch 16066 SHA256 02bfdb717629025e505c4575afe89c465ef47755223a5577842d6db3fef8e427 SHA512 d5a7590b95a1d8d4b2471ab7fb0f65fb9353b06ba0d5f5eb27a85ee870d8d57de169533fb43314eb7ce4a1c8b9ce1930077dbbbe31e1fe85b59fb9df844d299f WHIRLPOOL 3dbf7da6dda37e1e628dce1431455617eda08ea8200ef935da779057d9befffdc872718997d8f99b9afdca0284f77802daa449c68110e3dad56568a9c97251ce
+AUX phc-intel-0.3.2.12.1-2.6.36.patch 15934 SHA256 9310783980d12ababb1a5aaddd7ad2cf0c1f2f5a749a89cc32b33cfef9e49c28 SHA512 25e48428b8571138450e24779100199ff08bdb9346a68ff30a87015cb300923a62544ef87299bdab6b588d7d06a6ec0d5f0fd6638df279a5b7f9b3cd31c6c03a WHIRLPOOL d552cc5c521a98f73c66752a6c0ca9535c6031d903376eab58c4c5ca56cb6076247109c12c0a3a244ab2febac83ff87e2e480340a036246cfa9718c4cb500637
+AUX phc-intel-0.3.2.12.1-2.6.37.patch 15919 SHA256 3a58b6e56707a0b136507607818b8b58e106b1e5872c0b5b833fbddcb7c1d873 SHA512 5c9dc966a6a98718791cc28f83b7f52bd3faffb214a02c1db8e2d2cf8315b58d8505d3aa187abdef0391875d262510c7c3963ca9cbe8fd23ce8145a84cf5e6f9 WHIRLPOOL 33a54cfc2d6dd8d2019d48d2802269cc58b05e786c5a35d77e9be4a699edcc25696d4e10c40d630b70b0a51979ee9d4400bd0e8316a34a46863a4bb0955b200f
+AUX phc-intel-0.3.2.12.1-3.7.patch 16146 SHA256 f549c2ca3008e53b4f620255978bd155ee3a540e151d298495a056bc663ad692 SHA512 c66ec48b04d46ca3d20295322162c6a33b532bc0b4cb873c8033c6f3d2d8436a04099172f9f26208b8a6fbc1b10c3ab96f08aee3a03ac33bb0a6a22b1025a646 WHIRLPOOL 74a2e97f1e42313425da39bc404ac716cd85daf1d241ab596f53e27deae966eceaa8160eea0dd99034a0281519b662617d412856869dcb885c8c02b6ab18ff10
+DIST phc-intel-0.3.199.3_pre.tar.bz2 15508 SHA256 4441af7a0a1335a920b0d18a46483a64fbae8e57d98a6bdbf31dbacac2bbdf82
+DIST phc-intel-0.3.2.10.tar.bz2 20680 SHA256 8483e071ad2644c339539ac5298c7a31a12212fd9a68baa1f6766dad146510f5
+DIST phc-intel-0.3.2.12.1.tar.bz2 14412 SHA256 4f66989d424d328b205873da1b0363e75f27d7912e0e93c1cad3407c17be8264 SHA512 f9a63300fe1d7b42d1167c3b6d1f5b75cb707d8dac26d2d91f40466a26afedf3dccb76a58bb4764233ade6c309cdd554f869cdaeac04bf521607644afb709427 WHIRLPOOL dd064a2f5a67fc2aed96aa32bce4e040daf8468d2a215dbb08e11b00de039e7ac6179ea756a94035478a885a202f13517ec45a8dd8dfcd072436a0c8509e2fd0
+EBUILD phc-intel-0.3.199.3_pre.ebuild 1201 SHA256 cf022fadc97cd3b56ed3888b9f645d8943447a741627b2d80e19cb315147a1c0 SHA512 347b15195443ae14743eb44991a692bcc19ab50ddac83db769a7afcbc022330f0fd438a689797b3ff2da76a0297c6bb1f62ba3b4a4b772f6c56b96f3526462b7 WHIRLPOOL 976ecb939a0cd05922e6a6eb70854d5d9246ad9a6dd2ef45baf693fad40f6b27cab3273494b03a7badf34f1452b14283967210c5f97d3834e05220d7a6c4af4c
+EBUILD phc-intel-0.3.2.10.ebuild 1079 SHA256 19ed93eab1feeb9cd3aa214ba76ff5834cff06cb821676842574e6075f8a92c4 SHA512 038fa33588b9c2c57184f6978b36315841697d2b8fc91d4307336408623813d04bbef9fe17a940ef627b84bbcfb008111b823a11243af83b90c6928756b98551 WHIRLPOOL 670fd1c97f6dab85e7814b36c4b1d4b0f90ac6db0bba01d943f2d9d7b680f8e38aef84e5b6aa9d037f71d29b7cac955fd2d953815e7fdda4fe7ce96fd4488166
+EBUILD phc-intel-0.3.2.12.1-r3.ebuild 1696 SHA256 e1b3824ce44d78d60a9a906e10c4a4ddc28c9d0c4e2cdaf8afe536e956944fe0 SHA512 3b58991a343c10708baccf956104047ec24f343e053354f67dd7d861b5d5f70dd9f7a19f7ea62a0fd24ec4789dfbf9983fe923545b20f1c2d36755773a2e7121 WHIRLPOOL 504069347de21a785b4b3ed91b16c3854c3d01086898483a19cbf3189136dc191abf10cc4c75ea7755e1233d7bd70273c7880f8ae7d849a95a09d83073c6b8d0
+EBUILD phc-intel-0.3.2.12.1-r4.ebuild 1761 SHA256 236bc265725594d810184dbc2c313892a63d42b34e583b43bd9812f18521c6c1 SHA512 366adc050ff471faa0ba0c00d9419a8f0b8e0bf17b1155eddbd94a14f6c53afd9e4f22c50604fbb182790805f45bec2c1714df40d53e7506f4672fa57992b452 WHIRLPOOL b3478783a558b4c8f2edd5c21899165ba3f037e45f98a3af9ea07283d58396efc3f6be7ddc72d068707eb5db570cf41803df1c210576d608550607da27f6e8c8
+MISC ChangeLog 2093 SHA256 40203e4f3e00fdb8ae48dddebac480288dc667523515c6d2f9728174bae14ebc SHA512 45a7e12bad90c27b07a2cd0dbd5869c716bc6482a3c6db460bb6ec641c055720cd57e2e3bc3b419904b1b04a8c149f9806ba570f7f767b302e6ae5281418eb9e WHIRLPOOL 12a7e8dce55f434ebdecebf3111640dfe5b64976ee2fe8f471f1882ce45d1f2928d2b0186b946f86fda119823fd1d0fcd08191017787165a89b330f0d26c602b
+MISC metadata.xml 223 SHA256 89097f936927d56068988263e382edb683f359b27293955708e9ade4d256220d SHA512 c9f6a48b2aa05afdf73b8bd824c65480d76e54b659ca39928398c66f764d34faf186255d8aea034737424a962cf35151b610d078a01f8193b027c63e1e3c51b5 WHIRLPOOL 1ce20c98a7e177b8f510ef41f3935b0db5e04b2ecf465a683b2f2515f6a3043c33e6e9efc87f5aaaf59b2ed9be376d9d16bc8beff66b11aaa50ea899bfdc1f62
diff --git a/sys-power/phc-intel/files/phc-intel-0.3.2.12.1-3.7.patch b/sys-power/phc-intel/files/phc-intel-0.3.2.12.1-3.7.patch
new file mode 100644
index 000000000000..5d2949e92d46
--- /dev/null
+++ b/sys-power/phc-intel/files/phc-intel-0.3.2.12.1-3.7.patch
@@ -0,0 +1,534 @@
+--- hc-intel-0.3.2-12-1/phc-intel.c
++++ hc-intel-0.3.2-12-1/phc-intel.c
+@@ -25,6 +25,10 @@
+  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+  */
+ 
++/* This file has been patched with Linux PHC: www.linux-phc.org
++* Patch version: linux-phc-0.3.2
++*/
++
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/init.h>
+@@ -61,6 +65,10 @@ enum {
+ };
+ 
+ #define INTEL_MSR_RANGE		(0xffff)
++#define INTEL_MSR_VID_MASK	(0x00ff)
++#define INTEL_MSR_FID_MASK	(0xff00)
++#define INTEL_MSR_FID_SHIFT	(0x8)
++#define PHC_VERSION_STRING	"0.3.2:2"
+ #define AMD_MSR_RANGE		(0x7)
+ 
+ #define MSR_K7_HWCR_CPB_DIS	(1ULL << 25)
+@@ -70,6 +78,7 @@ struct acpi_cpufreq_data {
+ 	struct cpufreq_frequency_table *freq_table;
+ 	unsigned int resume;
+ 	unsigned int cpu_feature;
++	acpi_integer *original_controls;
+ };
+ 
+ static DEFINE_PER_CPU(struct acpi_cpufreq_data *, acfreq_data);
+@@ -222,17 +231,18 @@ static unsigned extract_io(u32 value, st
+ static unsigned extract_msr(u32 msr, struct acpi_cpufreq_data *data)
+ {
+ 	int i;
++	u32 fid;
+ 	struct acpi_processor_performance *perf;
+ 
+ 	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
+ 		msr &= AMD_MSR_RANGE;
+ 	else
+-		msr &= INTEL_MSR_RANGE;
++		fid = msr & INTEL_MSR_FID_MASK;
+ 
+ 	perf = data->acpi_data;
+ 
+ 	for (i = 0; data->freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
+-		if (msr == perf->states[data->freq_table[i].index].status)
++		if (fid == (perf->states[data->freq_table[i].index].status & INTEL_MSR_FID_MASK))
+ 			return data->freq_table[i].frequency;
+ 	}
+ 	return data->freq_table[0].frequency;
+@@ -868,6 +878,8 @@ static int acpi_cpufreq_cpu_init(struct
+ 	return result;
+ 
+ err_freqfree:
++	if (data->original_controls)
++		kfree(data->original_controls);
+ 	kfree(data->freq_table);
+ err_unreg:
+ 	acpi_processor_unregister_performance(perf, cpu);
+@@ -907,8 +919,471 @@ static int acpi_cpufreq_resume(struct cp
+ 	return 0;
+ }
+ 
++/* sysfs interface to change operating points voltages */
++
++static unsigned int extract_fid_from_control(unsigned int control)
++{
++	return ((control & INTEL_MSR_FID_MASK) >> INTEL_MSR_FID_SHIFT);
++}
++
++static unsigned int extract_vid_from_control(unsigned int control)
++{
++	return (control & INTEL_MSR_VID_MASK);
++}
++
++
++static bool check_cpu_control_capability(struct acpi_cpufreq_data *data) {
++ /* check if the cpu we are running on is capable of setting new control data
++  * 
++  */
++	if (unlikely(data == NULL || 
++	             data->acpi_data == NULL || 
++	             data->freq_table == NULL ||
++	             data->cpu_feature != SYSTEM_INTEL_MSR_CAPABLE)) {
++		return false;
++	} else {
++		return true;
++	};
++}
++
++
++static ssize_t check_origial_table (struct acpi_cpufreq_data *data)
++{
++
++	struct acpi_processor_performance *acpi_data;
++	struct cpufreq_frequency_table *freq_table;
++	unsigned int state_index;
++
++	acpi_data = data->acpi_data;
++	freq_table = data->freq_table;
++
++	if (data->original_controls == NULL) {
++		// Backup original control values
++		data->original_controls = kcalloc(acpi_data->state_count,
++		                                  sizeof(acpi_integer), GFP_KERNEL);
++		if (data->original_controls == NULL) {
++			printk("failed to allocate memory for original control values\n");
++			return -ENOMEM;
++		}
++		for (state_index = 0; state_index < acpi_data->state_count; state_index++) {
++			data->original_controls[state_index] = acpi_data->states[state_index].control;
++		}
++	}
++	return 0;
++}
++
++static ssize_t show_freq_attr_vids(struct cpufreq_policy *policy, char *buf)
++ /* display phc's voltage id's
++  * 
++  */
++{
++	struct acpi_cpufreq_data *data = per_cpu(acfreq_data, policy->cpu);
++	struct acpi_processor_performance *acpi_data;
++	struct cpufreq_frequency_table *freq_table;
++	unsigned int i;
++	unsigned int vid;
++	ssize_t count = 0;
++
++	if (!check_cpu_control_capability(data)) return -ENODEV; //check if CPU is capable of changing controls
++
++	acpi_data = data->acpi_data;
++	freq_table = data->freq_table;
++
++	for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
++		vid = extract_vid_from_control(acpi_data->states[freq_table[i].index].control);
++		count += sprintf(&buf[count], "%u ", vid);
++	}
++	count += sprintf(&buf[count], "\n");
++
++	return count;
++}
++
++static ssize_t show_freq_attr_default_vids(struct cpufreq_policy *policy, char *buf)
++ /* display acpi's default voltage id's
++  * 
++  */
++{
++	struct acpi_cpufreq_data *data = per_cpu(acfreq_data, policy->cpu);
++	struct cpufreq_frequency_table *freq_table;
++	unsigned int i;
++	unsigned int vid;
++	ssize_t count = 0;
++	ssize_t retval;
++
++	if (!check_cpu_control_capability(data)) return -ENODEV; //check if CPU is capable of changing controls
++
++	retval = check_origial_table(data);
++        if (0 != retval)
++		return retval; 
++
++	freq_table = data->freq_table;
++
++	for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
++		vid = extract_vid_from_control(data->original_controls[freq_table[i].index]);
++		count += sprintf(&buf[count], "%u ", vid);
++	}
++	count += sprintf(&buf[count], "\n");
++
++	return count;
++}
++
++static ssize_t show_freq_attr_fids(struct cpufreq_policy *policy, char *buf)
++ /* display phc's frequeny id's
++  * 
++  */
++{
++	struct acpi_cpufreq_data *data = per_cpu(acfreq_data, policy->cpu);
++	struct acpi_processor_performance *acpi_data;
++	struct cpufreq_frequency_table *freq_table;
++	unsigned int i;
++	unsigned int fid;
++	ssize_t count = 0;
++
++	if (!check_cpu_control_capability(data)) return -ENODEV; //check if CPU is capable of changing controls
++
++	acpi_data = data->acpi_data;
++	freq_table = data->freq_table;
++
++	for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
++		fid = extract_fid_from_control(acpi_data->states[freq_table[i].index].control);
++		count += sprintf(&buf[count], "%u ", fid);
++	}
++	count += sprintf(&buf[count], "\n");
++
++	return count;
++}
++
++static ssize_t show_freq_attr_controls(struct cpufreq_policy *policy, char *buf)
++ /* display phc's controls for the cpu (frequency id's and related voltage id's)
++  * 
++  */
++{
++	struct acpi_cpufreq_data *data = per_cpu(acfreq_data, policy->cpu);
++	struct acpi_processor_performance *acpi_data;
++	struct cpufreq_frequency_table *freq_table;
++	unsigned int i;
++	unsigned int fid;
++	unsigned int vid;
++	ssize_t count = 0;
++
++	if (!check_cpu_control_capability(data)) return -ENODEV; //check if CPU is capable of changing controls
++
++	acpi_data = data->acpi_data;
++	freq_table = data->freq_table;
++
++	for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
++		fid = extract_fid_from_control(acpi_data->states[freq_table[i].index].control);
++		vid = extract_vid_from_control(acpi_data->states[freq_table[i].index].control);
++		count += sprintf(&buf[count], "%u:%u ", fid, vid);
++	}
++	count += sprintf(&buf[count], "\n");
++
++	return count;
++}
++
++static ssize_t show_freq_attr_default_controls(struct cpufreq_policy *policy, char *buf)
++ /* display acpi's default controls for the cpu (frequency id's and related voltage id's)
++  * 
++  */
++{
++	struct acpi_cpufreq_data *data = per_cpu(acfreq_data, policy->cpu);
++	struct cpufreq_frequency_table *freq_table;
++	unsigned int i;
++	unsigned int fid;
++	unsigned int vid;
++	ssize_t count = 0;
++	ssize_t retval;
++
++	if (!check_cpu_control_capability(data)) return -ENODEV; //check if CPU is capable of changing controls
++
++	retval = check_origial_table(data);
++        if (0 != retval)
++		return retval; 
++
++	freq_table = data->freq_table;
++
++	for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
++		fid = extract_fid_from_control(data->original_controls[freq_table[i].index]);
++		vid = extract_vid_from_control(data->original_controls[freq_table[i].index]);
++		count += sprintf(&buf[count], "%u:%u ", fid, vid);
++	}
++	count += sprintf(&buf[count], "\n");
++
++	return count;
++}
++
++
++static ssize_t store_freq_attr_vids(struct cpufreq_policy *policy, const char *buf, size_t count)
++ /* store the voltage id's for the related frequency
++  * We are going to do some sanity checks here to prevent users 
++  * from setting higher voltages than the default one.
++  */
++{
++	struct acpi_cpufreq_data *data = per_cpu(acfreq_data, policy->cpu);
++	struct acpi_processor_performance *acpi_data;
++	struct cpufreq_frequency_table *freq_table;
++	unsigned int freq_index;
++	unsigned int state_index;
++	unsigned int new_vid;
++	unsigned int original_vid;
++	unsigned int new_control;
++	unsigned int original_control;
++	const char *curr_buf = buf;
++	char *next_buf;
++	ssize_t retval;
++
++	if (!check_cpu_control_capability(data)) return -ENODEV; //check if CPU is capable of changing controls
++
++	retval = check_origial_table(data);
++        if (0 != retval)
++		return retval; 
++
++	acpi_data = data->acpi_data;
++	freq_table = data->freq_table;
++
++	/* for each value taken from the sysfs interfalce (phc_vids) get entrys and convert them to unsigned long integers*/
++	for (freq_index = 0; freq_table[freq_index].frequency != CPUFREQ_TABLE_END; freq_index++) {
++		new_vid = simple_strtoul(curr_buf, &next_buf, 10);
++		if (next_buf == curr_buf) {
++			if ((curr_buf - buf == count - 1) && (*curr_buf == '\n')) {   //end of line?
++				curr_buf++;
++				break;
++			}
++			//if we didn't got end of line but there is nothing more to read something went wrong...
++			printk("failed to parse vid value at %i (%s)\n", freq_index, curr_buf);
++			return -EINVAL;
++		}
++
++		state_index = freq_table[freq_index].index;
++		original_control = data->original_controls[state_index];
++		original_vid = original_control & INTEL_MSR_VID_MASK;
++		
++		/* before we store the values we do some checks to prevent 
++		 * users to set up values higher than the default one
++		 */
++		if (new_vid <= original_vid) {
++			new_control = (original_control & ~INTEL_MSR_VID_MASK) | new_vid;
++			pr_debug("setting control at %i to %x (default is %x)\n",
++			        freq_index, new_control, original_control);
++			acpi_data->states[state_index].control = new_control;
++
++		} else {
++			pr_debug("skipping vid at %i, %u is greater than default %u\n",
++			       freq_index, new_vid, original_vid);
++		}
++
++		curr_buf = next_buf;
++		/* jump over value seperators (space or comma).
++		 * There could be more than one space or comma character
++		 * to separate two values so we better do it using a loop.
++		 */
++		while ((curr_buf - buf < count) && ((*curr_buf == ' ') || (*curr_buf == ','))) {
++			curr_buf++;
++		}
++	}
++
++	/* set new voltage for current frequency */
++	data->resume = 1;
++	acpi_cpufreq_target(policy, get_cur_freq_on_cpu(policy->cpu), CPUFREQ_RELATION_L);
++
++	return curr_buf - buf;
++}
++
++static ssize_t store_freq_attr_controls(struct cpufreq_policy *policy, const char *buf, size_t count)
++ /* store the controls (frequency id's and related voltage id's)
++  * We are going to do some sanity checks here to prevent users 
++  * from setting higher voltages than the default one.
++  */
++{
++	struct acpi_cpufreq_data *data = per_cpu(acfreq_data, policy->cpu);
++	struct acpi_processor_performance *acpi_data;
++	struct cpufreq_frequency_table *freq_table;
++	const char   *curr_buf;
++	unsigned int  op_count;
++	unsigned int  state_index;
++	int           isok;
++	char         *next_buf;
++	ssize_t       retval;
++	unsigned int  new_vid;
++	unsigned int  original_vid;
++	unsigned int  new_fid;
++	unsigned int  old_fid;
++	unsigned int  original_control;
++	unsigned int  old_control;
++	unsigned int  new_control;
++	int           found;
++
++	if (!check_cpu_control_capability(data)) return -ENODEV;
++
++	retval = check_origial_table(data);
++        if (0 != retval)
++		return retval;
++
++	acpi_data = data->acpi_data;
++	freq_table = data->freq_table;
++
++	op_count = 0;
++	curr_buf = buf;
++	next_buf = NULL;
++	isok     = 1;
++	
++	while ( (isok) && (curr_buf != NULL) )
++	{
++		op_count++;
++		// Parse fid
++		new_fid = simple_strtoul(curr_buf, &next_buf, 10);
++		if ((next_buf != curr_buf) && (next_buf != NULL))
++		{
++			// Parse separator between frequency and voltage 
++			curr_buf = next_buf;
++			next_buf = NULL;
++			if (*curr_buf==':')
++			{
++				curr_buf++;
++				// Parse vid
++				new_vid = simple_strtoul(curr_buf, &next_buf, 10);
++				if ((next_buf != curr_buf) && (next_buf != NULL))
++				{
++					found = 0;
++					for (state_index = 0; state_index < acpi_data->state_count; state_index++) {
++						old_control = acpi_data->states[state_index].control;
++						old_fid = extract_fid_from_control(old_control);
++						if (new_fid == old_fid)
++						{
++							found = 1;
++							original_control = data->original_controls[state_index];
++							original_vid = extract_vid_from_control(original_control);
++							if (new_vid <= original_vid)
++							{
++								new_control = (original_control & ~INTEL_MSR_VID_MASK) | new_vid;
++								pr_debug("setting control at %i to %x (default is %x)\n",
++								        state_index, new_control, original_control);
++								acpi_data->states[state_index].control = new_control;
++
++							} else {
++								printk("skipping vid at %i, %u is greater than default %u\n",
++								       state_index, new_vid, original_vid);
++							}
++						}
++					}
++
++					if (found == 0)
++					{
++						printk("operating point # %u not found (FID = %u)\n", op_count, new_fid);
++						isok = 0;
++					}
++
++					// Parse seprator before next operating point, if any
++					curr_buf = next_buf;
++					next_buf = NULL;
++					if ((*curr_buf == ',') || (*curr_buf == ' '))
++						curr_buf++;
++					else
++						curr_buf = NULL;
++				}
++				else
++				{
++					printk("failed to parse VID of operating point # %u (%s)\n", op_count, curr_buf);
++					isok = 0;
++				}
++			}
++			else
++			{
++				printk("failed to parse operating point # %u (%s)\n", op_count, curr_buf);
++				isok = 0;
++			}
++		}
++		else
++		{
++			printk("failed to parse FID of operating point # %u (%s)\n", op_count, curr_buf);
++			isok = 0;
++		}
++	}
++
++	if (isok)
++	{
++		retval = count;
++		/* set new voltage at current frequency */
++		data->resume = 1;
++		acpi_cpufreq_target(policy, get_cur_freq_on_cpu(policy->cpu), CPUFREQ_RELATION_L);
++	}
++	else
++	{
++		retval = -EINVAL;
++	}
++
++	return retval;
++}
++
++static ssize_t show_freq_attr_phc_version(struct cpufreq_policy *policy, char *buf)
++ /* print out the phc version string set at the beginning of that file
++  */
++{
++	ssize_t count = 0;
++	count += sprintf(&buf[count], "%s\n", PHC_VERSION_STRING);
++	return count;
++}
++
++
++
++static struct freq_attr cpufreq_freq_attr_phc_version =
++{
++	/*display phc's version string*/
++       .attr = { .name = "phc_version", .mode = 0444 },
++       .show = show_freq_attr_phc_version,
++       .store = NULL,
++};
++
++static struct freq_attr cpufreq_freq_attr_vids =
++{
++	/*display phc's voltage id's for the cpu*/
++       .attr = { .name = "phc_vids", .mode = 0644 },
++       .show = show_freq_attr_vids,
++       .store = store_freq_attr_vids,
++};
++
++static struct freq_attr cpufreq_freq_attr_default_vids =
++{
++	/*display acpi's default frequency id's for the cpu*/
++       .attr = { .name = "phc_default_vids", .mode = 0444 },
++       .show = show_freq_attr_default_vids,
++       .store = NULL,
++};
++
++static struct freq_attr cpufreq_freq_attr_fids =
++{
++	/*display phc's default frequency id's for the cpu*/
++       .attr = { .name = "phc_fids", .mode = 0444 },
++       .show = show_freq_attr_fids,
++       .store = NULL,
++};
++
++static struct freq_attr cpufreq_freq_attr_controls =
++{
++	/*display phc's current voltage/frequency controls for the cpu*/
++       .attr = { .name = "phc_controls", .mode = 0644 },
++       .show = show_freq_attr_controls,
++       .store = store_freq_attr_controls,
++};
++
++static struct freq_attr cpufreq_freq_attr_default_controls =
++{
++	/*display acpi's default voltage/frequency controls for the cpu*/
++       .attr = { .name = "phc_default_controls", .mode = 0444 },
++       .show = show_freq_attr_default_controls,
++       .store = NULL,
++};
++
++
++
+ static struct freq_attr *acpi_cpufreq_attr[] = {
+ 	&cpufreq_freq_attr_scaling_available_freqs,
++	&cpufreq_freq_attr_phc_version,
++	&cpufreq_freq_attr_vids,
++	&cpufreq_freq_attr_default_vids,
++	&cpufreq_freq_attr_fids,
++	&cpufreq_freq_attr_controls,
++	&cpufreq_freq_attr_default_controls,
+ 	NULL,	/* this is a placeholder for cpb, do not remove */
+ 	NULL,
+ };
diff --git a/sys-power/phc-intel/phc-intel-0.3.2.12.1-r4.ebuild b/sys-power/phc-intel/phc-intel-0.3.2.12.1-r4.ebuild
new file mode 100644
index 000000000000..e1d8f7f36d9e
--- /dev/null
+++ b/sys-power/phc-intel/phc-intel-0.3.2.12.1-r4.ebuild
@@ -0,0 +1,60 @@
+# Copyright 1999-2012 Gentoo Foundation
+# Distributed under the terms of the GNU General Public License v2
+# $Header: /var/cvsroot/gentoo-x86/sys-power/phc-intel/phc-intel-0.3.2.12.1-r4.ebuild,v 1.1 2012/11/15 01:08:43 xmw Exp $
+
+EAPI=2
+
+inherit linux-info linux-mod versionator eutils
+
+DESCRIPTION="Processor Hardware Control for Intel CPUs"
+HOMEPAGE="http://www.linux-phc.org/"
+SRC_URI="http://www.linux-phc.org/forum/download/file.php?id=94 -> ${P}.tar.bz2"
+
+LICENSE="GPL-2"
+SLOT="0"
+KEYWORDS="~amd64 ~x86"
+IUSE=""
+
+S=${WORKDIR}/${PN}-$(replace_version_separator 3 '-' $(replace_version_separator 4 '-'))
+
+CONFIG_CHECK="~!X86_ACPI_CPUFREQ"
+ERROR_X86_ACPI_CPUFREQ="CONFIG_X86_ACPI_CPUFREQ has to be configured to Module to enable the replacement of acpi-cpufreq with phc-intel."
+
+MODULE_NAMES="phc-intel(misc:)"
+BUILD_PARAMS="KERNELSRC=\"${KERNEL_DIR}\" -j1"
+BUILD_TARGETS="all"
+
+pkg_setup() {
+	if kernel_is lt 2 6 33 ; then
+		eerror "Your kernel version is no longer supported by this version of ${PN}."
+		eerror "Please use a previous version of ${PN} or a newer kernel."
+		die
+	fi
+	linux-mod_pkg_setup
+}
+
+src_prepare() {
+	sed -e '/^all:/s:prepare::' \
+		-e '/error Only support for 2.6 series kernels/d' \
+		-i Makefile || die
+
+	local my_sub=arch/x86/kernel/cpu
+	if kernel_is gt 2 6 39 ; then
+		my_sub=drivers
+	fi
+	cp -v "${KERNEL_DIR}"/${my_sub}/cpufreq/acpi-cpufreq.c phc-intel.c || die
+	cp -v "${KERNEL_DIR}"/${my_sub}/cpufreq/mperf.h . || die
+
+	if kernel_is eq 2 6 35 || kernel_is eq 2 6 36 ; then
+		epatch "${FILESDIR}"/${P}-${KV_MAJOR}.${KV_MINOR}.${KV_PATCH}.patch
+	elif kernel_is lt 3 7 ; then
+		epatch "${FILESDIR}"/${P}-2.6.37.patch
+	else
+		epatch "${FILESDIR}"/${P}-3.7.patch
+	fi
+}
+
+src_install() {
+	linux-mod_src_install
+	dodoc README || die
+}