New armv4t-nanojit patch as per request by armin76

Package-Manager: portage-2.2_rc67/cvs/Linux x86_64

4 files changed, 332 insertions, 14 deletions

diff --git a/net-libs/xulrunner/ChangeLog b/net-libs/xulrunner/ChangeLog
index 3ef7d764e717..53271b168bf2 100644
--- a/net-libs/xulrunner/ChangeLog
+++ b/net-libs/xulrunner/ChangeLog
@@ -1,6 +1,10 @@
 # ChangeLog for net-libs/xulrunner
 # Copyright 1999-2010 Gentoo Foundation; Distributed under the GPL v2
-# $Header: /var/cvsroot/gentoo-x86/net-libs/xulrunner/ChangeLog,v 1.349 2010/08/10 19:15:20 betelgeuse Exp $
+# $Header: /var/cvsroot/gentoo-x86/net-libs/xulrunner/ChangeLog,v 1.350 2010/08/13 15:00:06 polynomial-c Exp $
+
+  13 Aug 2010; Lars Wendler <polynomial-c@gentoo.org>
+  +files/1009-armv4t-nanojit-v2.patch, xulrunner-1.9.2.8-r1.ebuild:
+  New armv4t-nanojit patch as per request by armin76
 
   10 Aug 2010; Petteri Räty <betelgeuse@gentoo.org>
   xulrunner-1.9.2.8-r1.ebuild:
diff --git a/net-libs/xulrunner/Manifest b/net-libs/xulrunner/Manifest
index 4d9a8b5458a9..f1ce0536b50a 100644
--- a/net-libs/xulrunner/Manifest
+++ b/net-libs/xulrunner/Manifest
@@ -1,10 +1,8 @@
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 AUX 066-fix-includedir-mozilla-js.patch 747 RMD160 39c4430f77e42f5f5ad5f8038c036fccac1a7bb0 SHA1 9a1a09ee9bdca8ab9aeec6408baf207da9abe88a SHA256 069f6b1a43662e417e7f0194ceb039941c209409f8fb788914f862595cdf52f4
 AUX 1000_fix_alignment.patch 796 RMD160 d6098c483a90d47ead8cc7c643bf51270465b4cd SHA1 d2e861a0892550659a152d6a4ae9a1d31996c800 SHA256 49675bf2771b3e1bc50069f3a07f96062c771e8281d8e5abc2219dd08a23d377
 AUX 1002_fix-system-hunspell-dict-detections.patch 3394 RMD160 5db17109743eeff4550dd23c7780afb5eead6505 SHA1 3855eec6b3fc23652bb113ce4215555e7375566e SHA256 335e6f51c5e22ef8735c5a4c99b21b903f6d5dd32d6e766761c39a421ee651f3
+AUX 1009-armv4t-nanojit-v2.patch 12251 RMD160 9e9d862879d4897067605879245c1a6d50cf32fe SHA1 dcfe3da40dc822f2769e244571b721b59e59f322 SHA256 68c4df9c5313b93e8c5d7c7e8ed8375a88e9afa28c05e3965180058ba06cf05b
 AUX 301-xulrunner-xpctools.diff 550 RMD160 12d370d5473de5c54233a70533cd35e37305ef86 SHA1 e3812ce6a4446b0b9d496a9dd4760d03bf0de449 SHA256 6bf510f7df5a41f47501cbdbcffc46d0c04865e3597dc6a575cd4a9cfae1def4
 AUX 801-enable-x86_64-tracemonkey.patch 501 RMD160 e8341671a9ab7f05cf58735a2b862ded55d82829 SHA1 d0c194c79993c3c47a8c46726d3f024e044766a0 SHA256 20f558efbf4ed1960b390c353c7eeb94108fcdb8aaf33f1fea6caf44468aeb7c
 AUX xulrunner-1.9-no_sunstudio.patch 416 RMD160 fbd1be7182ff8a7aead935cf2f2ce5432aa5f5b8 SHA1 b50c3c30485ef140a0aeeb6de3875761cd906bcb SHA256 2dce8f5a07c623701ce5ae8c2517bd8776adff6c3a371d4762570e806ccf0a34
@@ -21,14 +19,7 @@ DIST firefox-3.6.8.source.tar.bz2 51238976 RMD160 14e245c643d41a1da25fe4dbc15d6a
 DIST xulrunner-1.9.2-patches-0.4.tar.bz2 5742 RMD160 d67504884a5959704d8cb2cfa7ff42401f328ac1 SHA1 3e1ba98046b9a4408e3eceb919ee9439ef328bdc SHA256 89db8d1cb166e97d56f911ebdfb8de852ab4335f137a4b7163345e8273a63d3f
 DIST xulrunner-1.9.2-patches-0.6.tar.bz2 16308 RMD160 6066ea0b01f8b6c9eae1a0692ad9a07f04ab7327 SHA1 ebba861e23ef36256dc29d7d04820222be8e4241 SHA256 6a9d709f9ee15d6c139a35f8a6826cd7b473188290bd5e81e56297d8f36e2235
 EBUILD xulrunner-1.9.2.4.ebuild 7191 RMD160 8633d7a9e174309d378bed99dcce757350a5e031 SHA1 f1da98486f1c78d5cb01da2e5b7174618e9694ea SHA256 9105361d24aec4de8f012180008d848b9672be2dc17fb8bc0762831381558149
-EBUILD xulrunner-1.9.2.8-r1.ebuild 7868 RMD160 5ef2663ca1d1efa83f6d3408ae2eb63c47ae0c02 SHA1 8c0a2c8871fb643793847ea97c34422555a6176c SHA256 3515c03314dac396cd748c79e7347b2d9fc3bc434a0c8ffa49e72d6047ee12a8
+EBUILD xulrunner-1.9.2.8-r1.ebuild 7968 RMD160 9a0ddf80238182e16d6441e072bccacdf28b248e SHA1 425762855347f1694dec37c00c6d4d096cd7159d SHA256 2a880c4810fda0d583ae2fab05c916655b248dd5accc55b89da11951e2f8b3c2
 EBUILD xulrunner-1.9.2.8.ebuild 7643 RMD160 f95763ac65fd5b2a6d658015c54ea0336b446a7a SHA1 7daef9f0173a34b4520826864361e86d723141f5 SHA256 eac5f7e525e4abf222b027367d19014ea9a69d1ee9a70fb2dcb9eef7d5ee7368
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diff --git a/net-libs/xulrunner/files/1009-armv4t-nanojit-v2.patch b/net-libs/xulrunner/files/1009-armv4t-nanojit-v2.patch
new file mode 100644
index 000000000000..2d57c95067a9
--- /dev/null
+++ b/net-libs/xulrunner/files/1009-armv4t-nanojit-v2.patch
@@ -0,0 +1,320 @@
+From: Mike Hommey <glandium@debian.org>
+Date: Fri, 30 Apr 2010 14:32:41 +0200
+Subject: Add nanojit support for ARMv4T
+
+Thanks Albin Tonnerre for the initial patch.
+https://bugzilla.mozilla.org/show_bug.cgi?id=552624
+---
+ js/src/nanojit/NativeARM.cpp |  105 ++++++++++++++++++++++------------------
+ js/src/nanojit/avmplus.h     |    2 +
+ js/src/nanojit/njcpudetect.h |  111 ++++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 170 insertions(+), 48 deletions(-)
+ create mode 100644 js/src/nanojit/njcpudetect.h
+
+diff --git a/js/src/nanojit/NativeARM.cpp b/js/src/nanojit/NativeARM.cpp
+index 9387191..a50898c 100644
+--- a/js/src/nanojit/NativeARM.cpp
++++ b/js/src/nanojit/NativeARM.cpp
+@@ -61,6 +61,8 @@ extern "C" void __clear_cache(void *BEG, void *END);
+ 
+ #ifdef FEATURE_NANOJIT
+ 
++#define ARM_ARCH_AT_LEAST(wanted) ((NJ_COMPILER_ARM_ARCH >= wanted) || (ARM_ARCH >= wanted))
++
+ namespace nanojit
+ {
+ 
+@@ -114,49 +116,50 @@ Assembler::CountLeadingZeroes(uint32_t data)
+ {
+     uint32_t    leading_zeroes;
+ 
+-    // We can't do CLZ on anything earlier than ARMv5. Architectures as early
+-    // as that aren't supported, but assert that we aren't running on one
+-    // anyway.
+-    // If ARMv4 support is required in the future for some reason, we can do a
+-    // run-time check on config.arch and fall back to the C routine, but for
+-    // now we can avoid the cost of the check as we don't intend to support
+-    // ARMv4 anyway.
+-    NanoAssert(ARM_ARCH >= 5);
+-
+ #if defined(__ARMCC__)
+     // ARMCC can do this with an intrinsic.
+     leading_zeroes = __clz(data);
+ 
+-// current Android GCC compiler incorrectly refuses to compile 'clz' for armv5
+-// (even though this is a legal instruction there). Since we currently only compile for ARMv5
+-// for emulation, we don't care too much (but we DO care for ARMv6+ since those are "real"
+-// devices).
+-#elif defined(__GNUC__) && !(defined(ANDROID) && __ARM_ARCH__ <= 5) 
++    if (0) // We don't need the fallback
++#elif defined(__GNUC__)
+     // GCC can use inline assembler to insert a CLZ instruction.
+-    __asm (
+-        "   clz     %0, %1  \n"
+-        :   "=r"    (leading_zeroes)
+-        :   "r"     (data)
+-    );
++    // Targetting armv5t allows a toolchain with armv4t default target to
++    // still build with clz. On Android gcc compiler, clz is not supported
++    // with a target smaller than armv7.
++    if (ARM_ARCH_AT_LEAST(5))
++        __asm (
++#if defined(ANDROID) && NJ_COMPILER_ARM_ARCH <= 5
++            ".arch armv7\n"
++#elif (NJ_COMPILER_ARM_ARCH < 5)
++            ".arch armv5t\n"
++#endif
++            "   clz     %0, %1  \n"
++            :   "=r"    (leading_zeroes)
++            :   "r"     (data)
++        );
++    else
+ #elif defined(WINCE)
+     // WinCE can do this with an intrinsic.
+     leading_zeroes = _CountLeadingZeros(data);
+-#else
+-    // Other platforms must fall back to a C routine. This won't be as
+-    // efficient as the CLZ instruction, but it is functional.
+-    uint32_t    try_shift;
+-
+-    leading_zeroes = 0;
+-
+-    // This loop does a bisection search rather than the obvious rotation loop.
+-    // This should be faster, though it will still be no match for CLZ.
+-    for (try_shift = 16; try_shift != 0; try_shift /= 2) {
+-        uint32_t    shift = leading_zeroes + try_shift;
+-        if (((data << shift) >> shift) == data) {
+-            leading_zeroes = shift;
++
++    if (0) // We don't need the fallback
++#endif
++    {
++        // Other platforms must fall back to a C routine. This won't be as
++        // efficient as the CLZ instruction, but it is functional.
++        uint32_t    try_shift;
++
++        leading_zeroes = 0;
++
++        // This loop does a bisection search rather than the obvious rotation loop.
++        // This should be faster, though it will still be no match for CLZ.
++        for (try_shift = 16; try_shift != 0; try_shift /= 2) {
++            uint32_t    shift = leading_zeroes + try_shift;
++            if (((data << shift) >> shift) == data) {
++                leading_zeroes = shift;
++            }
+         }
+     }
+-#endif
+ 
+     // Assert that the operation worked!
+     NanoAssert(((0xffffffff >> leading_zeroes) & data) == data);
+@@ -555,13 +558,18 @@ NIns*
+ Assembler::genEpilogue()
+ {
+     // On ARMv5+, loading directly to PC correctly handles interworking.
+-    // Note that we don't support anything older than ARMv5.
+-    NanoAssert(ARM_ARCH >= 5);
+-
+-    RegisterMask savingMask = rmask(FP) | rmask(PC);
++    // On ARMv4T, interworking is not handled properly, therefore, we pop
++    // lr into ip and use bx ip to avoid that.
++    if (ARM_ARCH_AT_LEAST(5)) {
++        RegisterMask savingMask = rmask(FP) | rmask(PC);
+ 
+-    POP_mask(savingMask); // regs
++        POP_mask(savingMask); // regs
++    } else {
++        RegisterMask savingMask = rmask(FP) | rmask(IP);
+ 
++        BX(IP);
++        POP_mask(savingMask); // regs
++    }
+     return _nIns;
+ }
+ 
+@@ -1502,7 +1510,7 @@ Assembler::BranchWithLink(NIns* addr)
+ 
+     // ARMv5 and above can use BLX <imm> for branches within ±32MB of the
+     // PC and BLX Rm for long branches.
+-    if (isS24(offs>>2)) {
++    if (isS24(offs>>2) && (ARM_ARCH_AT_LEAST(5))) {
+         // the value we need to stick in the instruction; masked,
+         // because it will be sign-extended back to 32 bits.
+         intptr_t offs2 = (offs>>2) & 0xffffff;
+@@ -1519,7 +1527,6 @@ Assembler::BranchWithLink(NIns* addr)
+             // We need to emit an ARMv5+ instruction, so assert that we have a
+             // suitable processor. Note that we don't support ARMv4(T), but
+             // this serves as a useful sanity check.
+-            NanoAssert(ARM_ARCH >= 5);
+ 
+             // The (pre-shifted) value of the "H" bit in the BLX encoding.
+             uint32_t    H = (offs & 0x2) << 23;
+@@ -1543,11 +1550,6 @@ Assembler::BranchWithLink(NIns* addr)
+ inline void
+ Assembler::BLX(Register addr, bool chk /* = true */)
+ {
+-    // We need to emit an ARMv5+ instruction, so assert that we have a suitable
+-    // processor. Note that we don't support ARMv4(T), but this serves as a
+-    // useful sanity check.
+-    NanoAssert(ARM_ARCH >= 5);
+-
+     NanoAssert(IsGpReg(addr));
+     // There is a bug in the WinCE device emulator which stops "BLX LR" from
+     // working as expected. Assert that we never do that!
+@@ -1558,8 +1560,15 @@ Assembler::BLX(Register addr, bool chk /* = true */)
+     }
+ 
+     // BLX IP
+-    *(--_nIns) = (NIns)( (COND_AL) | (0x12<<20) | (0xFFF<<8) | (0x3<<4) | (addr) );
+-    asm_output("blx ip");
++    if (ARM_ARCH_AT_LEAST(5)) {
++        *(--_nIns) = (NIns)( (COND_AL) | (0x12<<20) | (0xFFF<<8) | (0x3<<4) | (addr) );
++        asm_output("blx %s", gpn(addr));
++    } else {
++        *(--_nIns) = (NIns)( (COND_AL) | (0x12fff1 << 4) | (addr) );
++        asm_output("bx %s", gpn(addr));
++        *(--_nIns) = (NIns)( (COND_AL) | (0x1A0 << 16) | (0xE << 12) | 0xF );
++        asm_output("mov lr, pc");
++    }
+ }
+ 
+ // Emit the code required to load a memory address into a register as follows:
+@@ -2177,7 +2186,7 @@ Assembler::asm_arith(LInsp ins)
+             // common for (rr == ra) and is thus likely to be the most
+             // efficient case; if ra is no longer used after this LIR
+             // instruction, it is re-used for the result register (rr).
+-            if ((ARM_ARCH > 5) || (rr != rb)) {
++            if ((ARM_ARCH_AT_LEAST(6)) || (rr != rb)) {
+                 // Newer cores place no restrictions on the registers used in a
+                 // MUL instruction (compared to other arithmetic instructions).
+                 MUL(rr, rb, ra);
+diff --git a/js/src/nanojit/avmplus.h b/js/src/nanojit/avmplus.h
+index ffc0873..e86f22e 100644
+--- a/js/src/nanojit/avmplus.h
++++ b/js/src/nanojit/avmplus.h
+@@ -50,6 +50,8 @@
+ #include "jstypes.h"
+ #include "jsstdint.h"
+ 
++#include "njcpudetect.h"
++
+ #ifdef AVMPLUS_ARM
+ #define ARM_ARCH   config.arch
+ #define ARM_VFP    config.vfp
+diff --git a/js/src/nanojit/njcpudetect.h b/js/src/nanojit/njcpudetect.h
+new file mode 100644
+index 0000000..79ea90b
+--- /dev/null
++++ b/js/src/nanojit/njcpudetect.h
+@@ -0,0 +1,111 @@
++/* -*- Mode: C++; c-basic-offset: 4; indent-tabs-mode: nil; tab-width: 4 -*- */
++/* vi: set ts=4 sw=4 expandtab: (add to ~/.vimrc: set modeline modelines=5) */
++/* ***** BEGIN LICENSE BLOCK *****
++ * Version: MPL 1.1/GPL 2.0/LGPL 2.1
++ *
++ * The contents of this file are subject to the Mozilla Public License Version
++ * 1.1 (the "License"); you may not use this file except in compliance with
++ * the License. You may obtain a copy of the License at
++ * http://www.mozilla.org/MPL/
++ *
++ * Software distributed under the License is distributed on an "AS IS" basis,
++ * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License
++ * for the specific language governing rights and limitations under the
++ * License.
++ *
++ * The Original Code is [Open Source Virtual Machine].
++ *
++ * The Initial Developer of the Original Code is
++ * Adobe System Incorporated.
++ * Portions created by the Initial Developer are Copyright (C) 2004-2007
++ * the Initial Developer. All Rights Reserved.
++ *
++ * Contributor(s):
++ *   Adobe AS3 Team
++ *
++ * Alternatively, the contents of this file may be used under the terms of
++ * either the GNU General Public License Version 2 or later (the "GPL"), or
++ * the GNU Lesser General Public License Version 2.1 or later (the "LGPL"),
++ * in which case the provisions of the GPL or the LGPL are applicable instead
++ * of those above. If you wish to allow use of your version of this file only
++ * under the terms of either the GPL or the LGPL, and not to allow others to
++ * use your version of this file under the terms of the MPL, indicate your
++ * decision by deleting the provisions above and replace them with the notice
++ * and other provisions required by the GPL or the LGPL. If you do not delete
++ * the provisions above, a recipient may use your version of this file under
++ * the terms of any one of the MPL, the GPL or the LGPL.
++ *
++ * ***** END LICENSE BLOCK ***** */
++
++#ifndef __njcpudetect__
++#define __njcpudetect__
++
++/***
++ * Note: this file should not include *any* other files, nor should it wrap
++ * itself in ifdef FEATURE_NANOJIT, nor should it do anything other than
++ * define preprocessor symbols.
++ */
++
++/***
++ * NJ_COMPILER_ARM_ARCH attempts to specify the minimum ARM architecture
++ * that the C++ compiler has specified. Note that although Config::arm_arch
++ * is initialized to this value by default, there is no requirement that they
++ * be in sync.
++ *
++ * Note, this is done via #define so that downstream preprocessor usage can
++ * examine it, but please don't attempt to redefine it.
++ *
++ * Note, this is deliberately not encased in "ifdef NANOJIT_ARM", as this file
++ * may be included before that is defined. On non-ARM platforms we will hit the
++ * "Unable to determine" case.
++ */
++
++// GCC and RealView usually define __ARM_ARCH__
++#if defined(__ARM_ARCH__)
++
++    #define NJ_COMPILER_ARM_ARCH __ARM_ARCH__
++
++// ok, try well-known GCC flags ( see http://gcc.gnu.org/onlinedocs/gcc/ARM-Options.html )
++#elif     defined(__ARM_ARCH_7__) || \
++        defined(__ARM_ARCH_7A__) || \
++        defined(__ARM_ARCH_7M__) || \
++        defined(__ARM_ARCH_7R__) || \
++        defined(_ARM_ARCH_7)
++
++    #define NJ_COMPILER_ARM_ARCH 7
++
++#elif   defined(__ARM_ARCH_6__) || \
++        defined(__ARM_ARCH_6J__) || \
++        defined(__ARM_ARCH_6T2__) || \
++        defined(__ARM_ARCH_6Z__) || \
++        defined(__ARM_ARCH_6ZK__) || \
++        defined(__ARM_ARCH_6M__) || \
++        defined(_ARM_ARCH_6)
++
++    #define NJ_COMPILER_ARM_ARCH 6
++
++#elif   defined(__ARM_ARCH_5__) || \
++        defined(__ARM_ARCH_5T__) || \
++        defined(__ARM_ARCH_5E__) || \
++        defined(__ARM_ARCH_5TE__)
++
++    #define NJ_COMPILER_ARM_ARCH 5
++
++#elif   defined(__ARM_ARCH_4__) || \
++        defined(__ARM_ARCH_4T__)
++
++    #define NJ_COMPILER_ARM_ARCH 4
++
++// Visual C has its own mojo
++#elif defined(_MSC_VER) && defined(_M_ARM)
++
++    #define NJ_COMPILER_ARM_ARCH _M_ARM
++
++#else
++
++    // non-numeric value
++    #define NJ_COMPILER_ARM_ARCH "Unable to determine valid NJ_COMPILER_ARM_ARCH (nanojit only supports ARMv5 or later)"
++
++#endif
++
++#endif // __njcpudetect__
diff --git a/net-libs/xulrunner/xulrunner-1.9.2.8-r1.ebuild b/net-libs/xulrunner/xulrunner-1.9.2.8-r1.ebuild
index 34f583a6b8e0..85c0591fea0d 100644
--- a/net-libs/xulrunner/xulrunner-1.9.2.8-r1.ebuild
+++ b/net-libs/xulrunner/xulrunner-1.9.2.8-r1.ebuild
@@ -1,6 +1,6 @@
 # Copyright 1999-2010 Gentoo Foundation
 # Distributed under the terms of the GNU General Public License v2
-# $Header: /var/cvsroot/gentoo-x86/net-libs/xulrunner/xulrunner-1.9.2.8-r1.ebuild,v 1.4 2010/08/10 19:15:20 betelgeuse Exp $
+# $Header: /var/cvsroot/gentoo-x86/net-libs/xulrunner/xulrunner-1.9.2.8-r1.ebuild,v 1.5 2010/08/13 15:00:06 polynomial-c Exp $
 
 EAPI="3"
 WANT_AUTOCONF="2.1"
@@ -61,10 +61,13 @@ pkg_setup() {
 
 src_prepare() {
 	# Apply our patches
+	EPATCH_EXCLUDE="1009-armv4t-nanojit.patch" \
 	EPATCH_SUFFIX="patch" \
 	EPATCH_FORCE="yes" \
 	epatch "${WORKDIR}"
 
+	epatch "${FILESDIR}"/1009-armv4t-nanojit-v2.patch
+
 	eprefixify \
 		extensions/java/xpcom/interfaces/org/mozilla/xpcom/Mozilla.java \
 		xpcom/build/nsXPCOMPrivate.h \