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author | Denis Dupeyron <calchan@gentoo.org> | 2006-07-02 14:22:08 +0000 |
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committer | Denis Dupeyron <calchan@gentoo.org> | 2006-07-02 14:22:08 +0000 |
commit | 1e518d46d4cbe64472371d3f0ebace9080847dbd (patch) | |
tree | 0546e13ca4fa5a98d681b1ac59471fc6ed521517 /sci-electronics | |
parent | Stable on ppc; bug #138343. (diff) | |
download | gentoo-2-1e518d46d4cbe64472371d3f0ebace9080847dbd.tar.gz gentoo-2-1e518d46d4cbe64472371d3f0ebace9080847dbd.tar.bz2 gentoo-2-1e518d46d4cbe64472371d3f0ebace9080847dbd.zip |
Adjusted metadata, see bug #138062.
(Portage version: 2.1.1_pre1-r5)
Diffstat (limited to 'sci-electronics')
-rw-r--r-- | sci-electronics/iverilog/ChangeLog | 5 | ||||
-rw-r--r-- | sci-electronics/iverilog/metadata.xml | 11 |
2 files changed, 11 insertions, 5 deletions
diff --git a/sci-electronics/iverilog/ChangeLog b/sci-electronics/iverilog/ChangeLog index 94417039e65a..969cfb1ffd6b 100644 --- a/sci-electronics/iverilog/ChangeLog +++ b/sci-electronics/iverilog/ChangeLog @@ -1,6 +1,9 @@ # ChangeLog for sci-electronics/iverilog # Copyright 2002-2006 Gentoo Foundation; Distributed under the GPL v2 -# $Header: /var/cvsroot/gentoo-x86/sci-electronics/iverilog/ChangeLog,v 1.9 2006/03/11 20:53:40 halcy0n Exp $ +# $Header: /var/cvsroot/gentoo-x86/sci-electronics/iverilog/ChangeLog,v 1.10 2006/07/02 14:22:08 calchan Exp $ + + 02 Jul 2006; Denis Dupeyron <calchan@gentoo.org> metadata.xml: + Adjusted metadata, see bug #138062. 11 Mar 2006; Mark Loeser <halcy0n@gentoo.org> iverilog-0.8.2.ebuild: Fix patching diff --git a/sci-electronics/iverilog/metadata.xml b/sci-electronics/iverilog/metadata.xml index e2035cdbb121..ceafe325f3ef 100644 --- a/sci-electronics/iverilog/metadata.xml +++ b/sci-electronics/iverilog/metadata.xml @@ -1,8 +1,11 @@ <?xml version="1.0" encoding="UTF-8"?> <!DOCTYPE pkgmetadata SYSTEM "http://www.gentoo.org/dtd/metadata.dtd"> <pkgmetadata> -<herd>sci</herd> -<maintainer> - <email>plasmaroo@gentoo.org</email> -</maintainer> + <herd>sci-electronics</herd> + <longdescription> + Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a + compiler, compiling source code writen in Verilog (IEEE-1364) into some target + format. The compiler proper is intended to parse and elaborate design + descriptions written to the IEEE standard IEEE Std 1364-2001. + </longdescription> </pkgmetadata> |