From d6c73a0e6efb66f9d7b33069969b5ae86596cbeb Mon Sep 17 00:00:00 2001 From: Repository mirror & CI Date: Wed, 13 Jan 2021 04:42:02 +0000 Subject: 2021-01-13 04:42:01 UTC --- metadata/md5-cache/sci-electronics/systemc-2.3.4 | 13 ------------- metadata/md5-cache/sci-electronics/systemc-2.3.4-r1 | 14 ++++++++++++++ metadata/pkg_desc_index | 2 +- metadata/timestamp.chk | 2 +- 4 files changed, 16 insertions(+), 15 deletions(-) delete mode 100644 metadata/md5-cache/sci-electronics/systemc-2.3.4 create mode 100644 metadata/md5-cache/sci-electronics/systemc-2.3.4-r1 (limited to 'metadata') diff --git a/metadata/md5-cache/sci-electronics/systemc-2.3.4 b/metadata/md5-cache/sci-electronics/systemc-2.3.4 deleted file mode 100644 index ca2e7fcf7047..000000000000 --- a/metadata/md5-cache/sci-electronics/systemc-2.3.4 +++ /dev/null @@ -1,13 +0,0 @@ -BDEPEND=>=app-portage/elt-patches-20170815 || ( >=sys-devel/automake-1.16.2-r1:1.16 ) >=sys-devel/autoconf-2.69 >=sys-devel/libtool-2.4 -DEFINED_PHASES=configure postinst prepare -DESCRIPTION=A C++ based modeling platform for VLSI and system-level co-design -EAPI=7 -HOMEPAGE=https://accellera.org/community/systemc https://github.com/accellera-official/systemc -IUSE=debug static-libs test -KEYWORDS=~amd64 ~arm ~arm64 ~x86 -LICENSE=Apache-2.0 -RESTRICT=!test? ( test ) -SLOT=0 -SRC_URI=https://github.com/accellera-official/systemc/archive/2.3.4_pub_rev_20190614.tar.gz -> systemc-2.3.4.tar.gz -_eclasses_=autotools 9988ecbe04129214297a7bbf3d253710 libtool f143db5a74ccd9ca28c1234deffede96 multilib d410501a125f99ffb560b0c523cd3d1e toolchain-funcs 1a94dc06d324bd0dab754e11abe6d27e -_md5_=cf27b1b8ae92e1ff2fb9a577a1e28648 diff --git a/metadata/md5-cache/sci-electronics/systemc-2.3.4-r1 b/metadata/md5-cache/sci-electronics/systemc-2.3.4-r1 new file mode 100644 index 000000000000..5166ff80f7ba --- /dev/null +++ b/metadata/md5-cache/sci-electronics/systemc-2.3.4-r1 @@ -0,0 +1,14 @@ +BDEPEND=>=app-portage/elt-patches-20170815 || ( >=sys-devel/automake-1.16.2-r1:1.16 ) >=sys-devel/autoconf-2.69 >=sys-devel/libtool-2.4 +DEFINED_PHASES=configure install prepare +DESCRIPTION=A C++ based modeling platform for VLSI and system-level co-design +EAPI=7 +HOMEPAGE=https://accellera.org/community/systemc https://github.com/accellera-official/systemc +IUSE=debug doc examples static-libs test +KEYWORDS=~amd64 ~arm ~arm64 ~x86 +LICENSE=Apache-2.0 +REQUIRED_USE=examples? ( doc ) +RESTRICT=!test? ( test ) +SLOT=0 +SRC_URI=https://github.com/accellera-official/systemc/archive/2.3.4_pub_rev_20190614.tar.gz -> systemc-2.3.4.tar.gz +_eclasses_=autotools 9988ecbe04129214297a7bbf3d253710 libtool f143db5a74ccd9ca28c1234deffede96 multilib d410501a125f99ffb560b0c523cd3d1e toolchain-funcs 1a94dc06d324bd0dab754e11abe6d27e +_md5_=afc3b80b639f0b7967be9ddbe01fbb4f diff --git a/metadata/pkg_desc_index b/metadata/pkg_desc_index index b8e6a9de45e8..fb165d9923f0 100644 --- a/metadata/pkg_desc_index +++ b/metadata/pkg_desc_index @@ -16023,7 +16023,7 @@ sci-electronics/quartus-prime-lite 15.1.0.185-r2 15.1.0.185-r3: Full-featured ED sci-electronics/sigrok-cli 0.7.1-r1 9999: Command-line client for the sigrok logic analyzer software sci-electronics/spice 3.5.5-r2: general-purpose circuit simulation program sci-electronics/splat 1.4.2: RF Signal Propagation, Loss, And Terrain analysis tool -sci-electronics/systemc 2.3.1-r1 2.3.4: A C++ based modeling platform for VLSI and system-level co-design +sci-electronics/systemc 2.3.1-r1 2.3.4-r1: A C++ based modeling platform for VLSI and system-level co-design sci-electronics/vbs 1.4.0: vbs - the Verilog Behavioral Simulator sci-electronics/voacapl 0.7.2 0.7.6: HF propagation prediction tool sci-electronics/xcircuit 3.9.73: Circuit drawing and schematic capture program diff --git a/metadata/timestamp.chk b/metadata/timestamp.chk index 179604aae53d..c7f122a45f54 100644 --- a/metadata/timestamp.chk +++ b/metadata/timestamp.chk @@ -1 +1 @@ -Wed, 13 Jan 2021 04:12:49 +0000 +Wed, 13 Jan 2021 04:42:01 +0000 -- cgit v1.2.3-65-gdbad