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path: root/target-sparc/translate.c
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* global s/loglevel & X/qemu_loglevel_mask(X)/ (Eduardo Habkost)aliguori2009-01-151-2/+2
* Convert references to logfile/loglevel to use qemu_log*() macrosaliguori2009-01-151-9/+6
* Update FSF address in GPL/LGPL boilerplateaurel322009-01-041-1/+1
* Use sys-queue.h for break/watchpoint managment (Jan Kiszka)aliguori2008-11-251-2/+2
* Refactor and enhance break/watchpoint API (Jan Kiszka)aliguori2008-11-181-3/+4
* TCG variable type checking.pbrook2008-11-171-523/+521
* Use TCG not opblueswir12008-11-091-14/+12
* Use andc, orc, nor and nandblueswir12008-11-091-52/+36
* Fix TCGv size mismatchesblueswir12008-11-011-19/+21
* Implement UA2005 hypervisor trapsblueswir12008-09-261-2/+23
* Add software and timer interrupt supportblueswir12008-09-221-5/+29
* Use the new concat_tl_i64 op for std and stdablueswir12008-09-211-18/+6
* Use the new concat_i32_i64 op for std and stdablueswir12008-09-211-16/+20
* Fix mulscc with high bits set in either src1 or src2blueswir12008-09-131-2/+3
* Write zeros to high bits of y, based on patch by Vince Weaverblueswir12008-09-111-2/+4
* Convert rest of ops using float32 to TCG, remove FT0 and FT1blueswir12008-09-101-35/+16
* Partially convert float128 conversion ops to TCGblueswir12008-09-101-8/+6
* Convert basic 64 bit VIS ops to TCGblueswir12008-09-101-46/+65
* Convert basic 32 bit VIS ops to TCGblueswir12008-09-101-76/+38
* Convert basic float32 ops to TCGblueswir12008-09-101-150/+247
* Implement ldxfsr/stxfsr, fix ld(x)fsr masks, convert to TCGblueswir12008-09-091-8/+23
* Fix a typo in fpsub32blueswir12008-09-061-1/+1
* Convert most env fields to TCG registersblueswir12008-09-061-95/+91
* Silence gcc warning about constant overflowblueswir12008-09-061-2/+2
* Fix sign extension problems with smul and umul (Vince Weaver)blueswir12008-09-021-4/+4
* Fix y register loads and storesblueswir12008-09-011-18/+16
* Fix FCC handling for Sparc64 target, initial patch by Vince Weaverblueswir12008-08-291-4/+2
* Fix wrwim masking (Luis Pureza)blueswir12008-08-211-0/+3
* Use initial CPU definition structure for some CPU fields instead of copyingblueswir12008-08-211-10/+7
* Correct 32bit carry flag for add instruction (Igor Kovalenko)blueswir12008-08-171-5/+8
* Fix Sparc64 shiftsblueswir12008-08-061-5/+3
* Fix offset handling for ASI loads and stores (Vince Weaver)blueswir12008-08-061-3/+1
* Fix cmp/subcc/addcc op bugs reported by Vince Weaverblueswir12008-07-291-4/+4
* Make UA200x features selectable, add MMU typesblueswir12008-07-201-0/+6
* Implement nucleus quad lddablueswir12008-07-191-16/+12
* Small cleanup of gen_intermediate_code(_internal), by Laurent Desnogues.ths2008-07-181-7/+6
* wrhpr hstick_cmpr is a store, not a loadblueswir12008-07-181-3/+2
* Support for address maskingblueswir12008-07-171-22/+36
* Flushw can generate exceptions, so save PC & NPCblueswir12008-07-161-0/+1
* Really fix casblueswir12008-07-151-6/+5
* Add instruction counter.pbrook2008-06-291-1/+19
* Eliminate cpu_T[0]blueswir12008-06-221-9/+9
* Eliminate cpu_T[1]blueswir12008-06-221-4/+3
* Convert some cpu_dst uses (with loads/stores) to cpu_tmp0blueswir12008-06-211-67/+67
* Avoid brcond problems, use temps for cpu_src1 & cpu_src2blueswir12008-06-211-35/+32
* Avoid temporary variable use across basic blocks for udivxblueswir12008-06-151-2/+4
* Allow NWINDOWS selection (CPU feature with model specific defaults)blueswir12008-06-071-2/+0
* MicroSparc I didn't have fsmuld opblueswir12008-05-291-0/+1
* Free tempsblueswir12008-05-271-109/+313
* More TCG type fixesblueswir12008-05-261-11/+8