| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | [DAG] MatchRotate - bail if we fail to match a shl/srl pair |   Simon Pilgrim | 2022-08-25 | 1 | -0/+4 |
| * | [SDAG] avoid generating libcall to function with same name |   Sanjay Patel | 2022-08-22 | 1 | -1/+4 |
| * | [DAG] Ensure more Legal BUILD_VECTOR elements types in shuffle->And combine |   David Green | 2022-08-17 | 1 | -19/+25 |
| * | [DAGCombine] Check zext legality in zext-extract-extend combine |   Peter Waller | 2022-08-16 | 1 | -1/+2 |
| * | [DAG] Ensure Legal BUILD_VECTOR elements types in shuffle->And combine | David Green | 2022-08-10 | 1 | -0/+1 |
| * | [DAGCombiner] Extend visitAND to include EXTRACT_SUBVECTOR |   David Sherwood | 2022-08-09 | 1 | -0/+18 |
| * | [CodeGen] Fixed undeclared MISchedCutoff in case of NDEBUG and LLVM_ENABLE_AB...llvmorg-15.0.0-rc2 |   Dmitry Vassiliev | 2022-08-08 | 1 | -1/+1 |
| * | [DAG] matchRotateSub - ensure the (pre-extended) shift amount is wide enough ... | Simon Pilgrim | 2022-08-02 | 1 | -11/+15 |
| * | [CodeGen] Fixed ambiguous symbol ExtAddrMode in case of NDEBUG and LLVM_ENABL... | Dmitry Vassiliev | 2022-07-27 | 1 | -2/+2 |
| * | [MachineFunctionPass] Support -print-changed and -print-changed=quiet |   Fangrui Song | 2022-07-26 | 1 | -0/+29 |
| * | [DAG] matchRotateSub - set demanded bits to the shift amount type size, not t... | Simon Pilgrim | 2022-07-26 | 1 | -2/+4 |
| * | [WinEH] Apply funclet operand bundles to nounwind intrinsics that lower to fu... |   Stefan Gränitz | 2022-07-26 | 1 | -1/+6 |
| * | [SVE][SelectionDAG] Use INDEX to generate matching instances of BUILD_VECTOR. |   Paul Walker | 2022-07-26 | 1 | -0/+29 |
| * | [DAGCombine] Mask doesn't have to be (EltSize - 1) exactly when combining rot... |   wangpc | 2022-07-26 | 1 | -20/+20 |
| * | Reassoc FMF should not optimize FMA(a, 0, b) to (b) |   Sven van Haastregt | 2022-07-26 | 1 | -4/+5 |
| * | Remove redundaunt virtual specifiers (NFC) |   Kazu Hirata | 2022-07-25 | 1 | -1/+1 |
| * | [DAGCombiner] Teach scalarizeExtractedBinop to support scalable splat. |   jacquesguan | 2022-07-26 | 1 | -4/+7 |
| * | [GlobalISel] Fix miscompile of G_UREM + G_UDIV due to not checking for equality |   Amara Emerson | 2022-07-25 | 1 | -1/+2 |
| * | [IRBuilder] Add assert for AtomicRMW ordering |   Alexander Shaposhnikov | 2022-07-25 | 1 | -1/+6 |
| * | RegAllocGreedy: Add a command line flag for reverseLocalAssignment |   Matt Arsenault | 2022-07-25 | 2 | -5/+16 |
| * | [GlobalISel][DebugInfo] Remove debug info with zero line from constants inser... |   Vladislav Dzhidzhoev | 2022-07-25 | 1 | -6/+4 |
| * | [AsmPrinter] Reject ptrtoint to larger size in lowerConstant() |   Nikita Popov | 2022-07-25 | 1 | -6/+1 |
| * | [llvm] Remove redundaunt virtual specifiers (NFC) | Kazu Hirata | 2022-07-24 | 2 | -2/+2 |
| * | Use llvm::less_first and llvm::less_second (NFC) | Kazu Hirata | 2022-07-24 | 1 | -2/+1 |
| * | [CodeGen] Remove a redundant void (NFC) | Kazu Hirata | 2022-07-24 | 1 | -1/+1 |
| * | RegAllocGreedy: Fix subranges when rematerializing dead subreg defs | Matt Arsenault | 2022-07-24 | 1 | -2/+14 |
| * | [DAG] visitSMUL_LOHI/visitUMUL_LOHI - ensure we canonicalize constants to the... | Simon Pilgrim | 2022-07-24 | 1 | -7/+21 |
| * | [DAG] getNode - assert that SMUL_LOHI/UMUL_LOHI nodes have the correct ops + ... | Simon Pilgrim | 2022-07-24 | 1 | -0/+9 |
| * | [DAG] MaskedVectorIsZero - don't bother with (-1).isSubsetOf mask check. NFC. | Simon Pilgrim | 2022-07-24 | 1 | -2/+1 |
| * | [DAG] SimplifyMultipleUseDemandedBits - early-out for any scalable vector types | Simon Pilgrim | 2022-07-24 | 1 | -1/+16 |
| * | [DAG] SimplifyDemandedVectorElts - if every and/mul element-pair has a zero/u... | Simon Pilgrim | 2022-07-24 | 1 | -1/+6 |
| * | [CodeGen] Use range-based for loops (NFC) | Kazu Hirata | 2022-07-23 | 1 | -2/+1 |
| * | [DAG] isSplatValue - don't attempt to merge any BITCAST sub elements if they ... | Simon Pilgrim | 2022-07-23 | 1 | -10/+3 |
| * | Use llvm::sort instead of std::sort where possible |   Dmitri Gribenko | 2022-07-23 | 1 | -4/+3 |
| * | [DAG] Move OR(AND(X,C1),AND(OR(X,Y),C2)) -> OR(AND(X,OR(C1,C2)),AND(Y,C2)) fo... | Simon Pilgrim | 2022-07-23 | 2 | -21/+27 |
| * | [DAG] SimplifyDemandedBits - pull out repeated getValueType() calls. NFC. | Simon Pilgrim | 2022-07-23 | 1 | -4/+3 |
| * | [DAG] ExpandIntRes_ADDSUB - create UADDO/USUBO instead of ADDCARRY/SUBCARRY i... | Simon Pilgrim | 2022-07-23 | 1 | -2/+6 |
| * | [DAG] computeKnownBits - add basic shift-by-parts handling | Simon Pilgrim | 2022-07-23 | 1 | -0/+32 |
| * | Add a nop instruction if a section starts with landing pad for function splitter |   ARCHIT SAXENA | 2022-07-22 | 2 | -5/+3 |
| * | [DAGCombiner] Simplify code around call to reduceLoadWidth in visitAND. NFC |   Craig Topper | 2022-07-22 | 1 | -12/+3 |
| * | [AsmPrinter] Move lowerConstant() error code out of switch (NFC) | Nikita Popov | 2022-07-22 | 1 | -18/+18 |
| * | [AArch64] Emit vector FP cmp when LE is used with fast-math |   Cullen Rhodes | 2022-07-22 | 1 | -0/+9 |
| * | recommit "[DAGCombiner] Teach scalarizeBinOpOfSplats handle scalable splat." | jacquesguan | 2022-07-21 | 1 | -1/+7 |
| * | [SelectionDAG] Fix fptoi.sat scalable vector lowering | David Green | 2022-07-21 | 2 | -2/+31 |
| * | [AIX] follow-up of D124654. |   esmeyi | 2022-07-21 | 1 | -3/+6 |
| * | [DAG] getNode - don't bother creating ADDO(X,0) or SUBO(X,0) nodes. | Simon Pilgrim | 2022-07-20 | 1 | -1/+12 |
| * | [DAG] getNode - assert that ADDO/SUBO nodes have the correct ops + types | Simon Pilgrim | 2022-07-20 | 1 | -0/+11 |
| * | [DAG] PromoteIntRes_BUILD_VECTOR - extend constant boolean vectors according ... | Simon Pilgrim | 2022-07-20 | 1 | -6/+13 |
| * | [VP] Legalize the stride operand for EXPERIMENTAL_VP_STRIDED SDNodes |   Lorenzo Albano | 2022-07-20 | 2 | -0/+31 |
| * | [llvm] Use llvm::any_of and llvm::none_of (NFC) | Kazu Hirata | 2022-07-20 | 2 | -6/+8 |
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