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authorDavid Stuttard <david.stuttard@amd.com>2022-08-09 08:46:55 +0100
committerTobias Hieta <tobias@hieta.se>2022-09-07 08:37:18 +0200
commitdca7f087109debc1f376946dc244ed5d7e27a257 (patch)
treed35b946d24977435d2101f70d805965befb732f1 /llvm/lib/CodeGen
parent[RISCV][ReleaseNotes] Added LLVM and Clang release notes for RISC-V 15.0.0 (diff)
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AMDGPU: mbcnt allow for non-zero src1 for known-bits
Src1 for mbcnt can be a non-zero literal or register. Take this into account when calculating known bits. Differential Revision: https://reviews.llvm.org/D131478 (cherry picked from commit 1d1cc05539e275ae7666fc4b44bf725ec335078a)
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