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author | David Stuttard <david.stuttard@amd.com> | 2022-08-09 08:46:55 +0100 |
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committer | Tobias Hieta <tobias@hieta.se> | 2022-09-07 08:37:18 +0200 |
commit | dca7f087109debc1f376946dc244ed5d7e27a257 (patch) | |
tree | d35b946d24977435d2101f70d805965befb732f1 /llvm/lib/CodeGen | |
parent | [RISCV][ReleaseNotes] Added LLVM and Clang release notes for RISC-V 15.0.0 (diff) | |
download | llvm-project-dca7f087109debc1f376946dc244ed5d7e27a257.tar.gz llvm-project-dca7f087109debc1f376946dc244ed5d7e27a257.tar.bz2 llvm-project-dca7f087109debc1f376946dc244ed5d7e27a257.zip |
AMDGPU: mbcnt allow for non-zero src1 for known-bits
Src1 for mbcnt can be a non-zero literal or register. Take this into account
when calculating known bits.
Differential Revision: https://reviews.llvm.org/D131478
(cherry picked from commit 1d1cc05539e275ae7666fc4b44bf725ec335078a)
Diffstat (limited to 'llvm/lib/CodeGen')
0 files changed, 0 insertions, 0 deletions