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path: root/gas/doc/c-i386.texi
Commit message (Expand)AuthorAgeFilesLines
* x86: introduce a state stack for .archJan Beulich2022-07-061-1/+1
* x86: permit "default" with .archJan Beulich2022-07-061-1/+2
* x86: drop L1OM/K1OM support from gasJan Beulich2022-03-171-3/+1
* Update year range in copyright notice of binutils filesAlan Modra2022-01-021-1/+1
* x86: Add -muse-unaligned-vector-move to assemblerH.J. Lu2021-10-221-0/+6
* x86: introduce .bfloat16 directiveJan Beulich2021-08-111-6/+8
* x86: introduce .hfloat directiveJan Beulich2021-08-111-5/+8
* [PATCH 1/2] Enable Intel AVX512_FP16 instructionsCui,Lili2021-08-051-1/+3
* i386: Replace movsb with movsxbSebastien Villemot2021-05-261-1/+1
* PR27116, Spelling errors found by Debian style checkerAlan Modra2021-01-011-1/+1
* Update year range in copyright notice of binutils filesAlan Modra2021-01-011-1/+1
* gas: Update 80387 floating point 's' suffixH.J. Lu2020-12-251-1/+1
* Add AMD znver3 processor supportGanesh Gopalasubramanian2020-10-201-3/+8
* x86: Support Intel AVX VNNIH.J. Lu2020-10-141-1/+7
* x86: Add support for Intel HRESET instructionLili Cui2020-10-141-1/+3
* x86: Support Intel UINTRLili Cui2020-10-141-1/+3
* Add support for Intel TDX instructions.Cui,Lili2020-09-241-0/+3
* Enable support to Intel Keylocker instructionsTerry Guo2020-09-231-0/+5
* x86: Add {disp16} pseudo prefixH.J. Lu2020-07-301-1/+4
* x86: Handle {disp32} for (%bp)/(%ebp)/(%rbp)H.J. Lu2020-07-281-1/+1
* x86: Add support for Intel AMX instructionsLili Cui2020-07-101-0/+7
* x86: Remove an incorrect AVX2 entryH.J. Lu2020-07-071-10/+0
* x86: Correct noavx512_vp2intersectCui,Lili2020-06-161-0/+1
* x86: Add i386 PE big-object supportTamar Christina2020-04-271-1/+2
* Improve -mlfence-after-loadliuhongt2020-04-261-4/+8
* x86: Correct -mlfence-before-indirect-branch= documentationH.J. Lu2020-04-081-3/+3
* Add support for intel TSXLDTRK instructions$Cui,Lili2020-04-071-1/+3
* Add support for intel SERIALIZE instructionLiliCui2020-04-021-0/+2
* i386: Generate lfence with load/indirect branch/ret [CVE-2020-0551]H.J. Lu2020-03-111-0/+43
* x86: support VMGEXITJan Beulich2020-03-041-1/+2
* x86: Remove CpuABM and add CpuPOPCNTH.J. Lu2020-02-171-5/+6
* x86: Don't disable SSE4a when disabling SSE4H.J. Lu2020-02-161-1/+3
* Remove the old movsx and movzx documentation for AT&T syntaxH.J. Lu2020-02-141-16/+0
* x86: Document movsx/movsxd/movzx for AT&T syntaxH.J. Lu2020-02-141-0/+53
* x86-64: Intel64 adjustments for insns dealing with far pointersJan Beulich2020-02-121-0/+12
* x86: Accept Intel64 only instruction by defaultH.J. Lu2020-02-101-1/+2
* x86-64: Properly encode and decode movsxdH.J. Lu2020-01-271-0/+18
* x86: improve handling of insns with ambiguous operand sizesJan Beulich2020-01-211-0/+25
* x86: Add {vex} pseudo prefixH.J. Lu2020-01-171-2/+2
* Update year range in copyright notice of binutils filesAlan Modra2020-01-011-1/+1
* i386: Add -mbranches-within-32B-boundariesH.J. Lu2019-12-121-0/+11
* i386: Align branches within a fixed boundaryH.J. Lu2019-12-121-0/+26
* x86: support further AMD Zen2 instructionsJan Beulich2019-11-071-1/+4
* Document the .value directive supported by the x86 and x86_64 assemblers.Nick Clifton2019-07-011-0/+6
* x86: optimize AND/OR with twice the same registerJan Beulich2019-07-011-1/+2
* x86-64: optimize certain commutative VEX-encoded insnsJan Beulich2019-07-011-1/+4
* x86: optimize EVEX packed integer logical instructionsJan Beulich2019-07-011-6/+10
* i386: Document memory size reference in assemblerLili Cui2019-06-261-5/+10
* x86: document certain command line options as "dangerous"Jan Beulich2019-06-251-0/+6
* gas: Add .enqcmd and noenqcmd directivesH.J. Lu2019-06-061-0/+1